On Mon, Jun 05, 2017 at 09:04:26PM +0300, Ville Syrjälä wrote:
> On Mon, Jun 05, 2017 at 05:59:02PM +0000, Vivi, Rodrigo wrote:
> > On Fri, 2017-06-02 at 21:06 +0300, Imre Deak wrote:
> > > > [...]
> > > > +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> > > > + struct intel_cdclk_state *cdclk_state)
> > > > +{
> > > > + u32 val;
> > > > +
> > > > + if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> > > > + cdclk_state->ref = 24000;
> > > > + else
> > > > + cdclk_state->ref = 19200;
> > > > +
> > > > + cdclk_state->vco = 0;
> > > > +
> > > > + val = I915_READ(BXT_DE_PLL_ENABLE);
> > > > + if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> > > > + return;
> > > > +
> > > > + if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> > > > + return;
> > > > +
> > > > + cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
> > > > +}
> > > > +
> > > > +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> > > > + struct intel_cdclk_state *cdclk_state)
> > > > +{
> > > > + u32 divider;
> > > > + int div;
> > > > +
> > > > + cnl_cdclk_pll_update(dev_priv, cdclk_state);
> > >
> > > The other platforms set cdclk to the ref clock here, not sure
> > > if it's ok to leave it uninited. With that change it looks ok:
> >
> > Not sure how to address this here...
> > I see bxt and skl using the cdclk_state here...
>
> Assuming refclk is the bypass clock then just doing what the earlier
> platforms do would be correct.
Yes, according to Bspec the CDCLK freq is the refclock freq when the PLL
is disabled.
> IIRC there was some platform where the bypass clock wasn't the refclk,
> but that was perhaps some future thing. Either way, whatever the
> bypass clock is we will want the readout to correctly reflect it when
> the PLL is off.
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