Re: [PATCH] drm/i915/cnp: add CNP gmbus support

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>-----Original Message-----
>From: Rodrigo Vivi [mailto:rodrigo.vivi@xxxxxxxxx]
>Sent: Wednesday, May 31, 2017 11:29 AM
>To: Vivi, Rodrigo <rodrigo.vivi@xxxxxxxxx>; Srivatsa, Anusha
><anusha.srivatsa@xxxxxxxxx>
>Cc: intel-gfx <intel-gfx@xxxxxxxxxxxxxxxxxxxxx>; Nikula, Jani
><jani.nikula@xxxxxxxxx>; Vetter, Daniel <daniel.vetter@xxxxxxxxx>
>Subject: Re:  [PATCH] drm/i915/cnp: add CNP gmbus support
>
>Anusha, when going to merge I noticed that we had the wrong version here.
>
>The incorrect version would break hdmi on CFL. The right workaround is not to
>respect the CNL bios for the pin number.
>
>So, I hope I can keep your rv-b on this one, but I'd like you to confirm please.

Looked into the spec again. You are right, mapping has to be changed.

Anusha 

>Thanks,
>Rodrigo.
>
>On Wed, May 31, 2017 at 11:26 AM, Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
>wrote:
>> On CNP PCH based platforms the gmbus is on the south display that is
>> on PCH. The existing implementation for previous platforms already
>> covers the need for CNP expect for the pin pair configuration that
>> follows similar definitions that we had on BXT.
>>
>> v2: Don't drop "_BXT" as the indicator of the first platform
>>     supporting this pin numbers. Suggested by Daniel.
>> v3: Add missing else and fix register table since CNP GPIO_CTL
>>     starts on 0xC5014.
>> v4: Fix pin number and map according to the current available VBT.
>>     Re-add pin 4 for port D. Lost during some rebase.
>> v5: Use table as spec. If VBT is wrong it should be ignored.
>>
>> Cc: Daniel Vetter <daniel.vetter@xxxxxxxxx>
>> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h   |  3 ++-
>>  drivers/gpu/drm/i915/intel_hdmi.c |  8 +++++---
>> drivers/gpu/drm/i915/intel_i2c.c  | 15 +++++++++++++--
>>  3 files changed, 20 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 6826547..efbbeb8 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2618,9 +2618,10 @@ enum skl_disp_power_wells {
>>  #define   GMBUS_PIN_DPB                5 /* SDVO, HDMIB */
>>  #define   GMBUS_PIN_DPD                6 /* HDMID */
>>  #define   GMBUS_PIN_RESERVED   7 /* 7 reserved */
>> -#define   GMBUS_PIN_1_BXT      1
>> +#define   GMBUS_PIN_1_BXT      1 /* BXT+ (atom) and CNP+ (big core) */
>>  #define   GMBUS_PIN_2_BXT      2
>>  #define   GMBUS_PIN_3_BXT      3
>> +#define   GMBUS_PIN_4_CNP      4
>>  #define   GMBUS_NUM_PINS       7 /* including 0 */
>>  #define GMBUS1                 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /*
>command/status */
>>  #define   GMBUS_SW_CLR_INT     (1<<31)
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
>> b/drivers/gpu/drm/i915/intel_hdmi.c
>> index 6efc3cb..f8c40ae 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -1892,19 +1892,21 @@ static u8 intel_hdmi_ddc_pin(struct
>> drm_i915_private *dev_priv,
>>
>>         switch (port) {
>>         case PORT_B:
>> -               if (IS_GEN9_LP(dev_priv))
>> +               if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
>>                         ddc_pin = GMBUS_PIN_1_BXT;
>>                 else
>>                         ddc_pin = GMBUS_PIN_DPB;
>>                 break;
>>         case PORT_C:
>> -               if (IS_GEN9_LP(dev_priv))
>> +               if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
>>                         ddc_pin = GMBUS_PIN_2_BXT;
>>                 else
>>                         ddc_pin = GMBUS_PIN_DPC;
>>                 break;
>>         case PORT_D:
>> -               if (IS_CHERRYVIEW(dev_priv))
>> +               if (HAS_PCH_CNP(dev_priv))
>> +                       ddc_pin = GMBUS_PIN_4_CNP;
>> +               else if (IS_CHERRYVIEW(dev_priv))
>>                         ddc_pin = GMBUS_PIN_DPD_CHV;
>>                 else
>>                         ddc_pin = GMBUS_PIN_DPD; diff --git
>> a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
>> index b6401e8..3c9e00d 100644
>> --- a/drivers/gpu/drm/i915/intel_i2c.c
>> +++ b/drivers/gpu/drm/i915/intel_i2c.c
>> @@ -68,11 +68,20 @@ struct gmbus_pin {
>>         [GMBUS_PIN_3_BXT] = { "misc", GPIOD },  };
>>
>> +static const struct gmbus_pin gmbus_pins_cnp[] = {
>> +       [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
>> +       [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
>> +       [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
>> +       [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, };
>> +
>>  /* pin is expected to be valid */
>>  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
>*dev_priv,
>>                                              unsigned int pin)  {
>> -       if (IS_GEN9_LP(dev_priv))
>> +       if (HAS_PCH_CNP(dev_priv))
>> +               return &gmbus_pins_cnp[pin];
>> +       else if (IS_GEN9_LP(dev_priv))
>>                 return &gmbus_pins_bxt[pin];
>>         else if (IS_GEN9_BC(dev_priv))
>>                 return &gmbus_pins_skl[pin]; @@ -87,7 +96,9 @@ bool
>> intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,  {
>>         unsigned int size;
>>
>> -       if (IS_GEN9_LP(dev_priv))
>> +       if (HAS_PCH_CNP(dev_priv))
>> +               size = ARRAY_SIZE(gmbus_pins_cnp);
>> +       else if (IS_GEN9_LP(dev_priv))
>>                 size = ARRAY_SIZE(gmbus_pins_bxt);
>>         else if (IS_GEN9_BC(dev_priv))
>>                 size = ARRAY_SIZE(gmbus_pins_skl);
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
>--
>Rodrigo Vivi
>Blog: http://blog.vivi.eng.br
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