On Thu, Apr 06, 2017 at 12:15:46PM -0700, Rodrigo Vivi wrote:
> From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
>
> Gen 10 should use the exact same code as Gen 9, so change the check to
> take this into consideration, and also assume that future platforms
> will run this code.
>
> Also add a MISSING_CASE(), just in case we do something wrong, instead
> of silently failing.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4c07b91..a2b2509 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2291,7 +2291,7 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
> static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
> uint16_t wm[8])
> {
> - if (IS_GEN9(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> uint32_t val;
> int ret, i;
> int level, max_level = ilk_wm_max_level(dev_priv);
> @@ -2351,7 +2351,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
> }
>
> /*
> - * WaWmMemoryReadLatency:skl,glk
> + * WaWmMemoryReadLatency:skl+,glk
When we did we start to use the '+' notation in the w/a notes?
What would it mean to say 'skl+,glk'? Is BXT included or not?
> *
> * punit doesn't take into account the read latency so we need
> * to add 2us to the various latency levels we retrieve from the
> @@ -2390,6 +2390,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
> wm[0] = 7;
> wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
> wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
> + } else {
> + MISSING_CASE(INTEL_DEVID(dev_priv));
> }
> }
>
> --
> 1.9.1
>
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--
Ville Syrjälä
Intel OTC
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