Slice shutdown override interface (i915_slice_enabled) permits
to power on/off GPGPU slices in Gen8 and Gen9. This is helpful
in performance investigations amd checking scalability across
hw platforms. Changes to slice number done via this interface
will effect any lrc created after the write and will not affect
older ones.
v1: Restrict effect of the patch to SKL. Comment code.
Change-Id: I4f2fe5fefb8d1df4519fd0eb58237759c7d1a930
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@xxxxxxxxx>
CC: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
CC: Zhipeng Gong <zhipeng.gong@xxxxxxxxx>
CC: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
CC: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_debugfs.c | 38 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
4 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d689e51..4d7dac5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4812,6 +4812,41 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
{"i915_drrs_status", i915_drrs_status, 0},
{"i915_rps_boost_info", i915_rps_boost_info, 0},
};
+
+static int
+i915_slice_enabled_get(void *data, u64 *val)
+{
+ struct drm_i915_private *dev_priv = data;
+
+ *val = INTEL_INFO(dev_priv)->sseu.slice_enabled;
+ return 0;
+}
+
+/* Changes to slice number done via this interface will effect
+ * any lrc created after the write and will not affect
+ * older ones.
+ */
+static int
+i915_slice_enabled_set(void *data, u64 val)
+{
+ struct drm_i915_private *dev_priv = data;
+ struct intel_device_info *info;
+
+ info = mkwrite_device_info(dev_priv);
+ if (!IS_SKYLAKE(dev_priv) || !info->sseu.has_slice_pg)
+ return -EINVAL;
+
+ if (val > hweight8(info->sseu.slice_mask))
+ return -EINVAL;
+
+ info->sseu.slice_enabled = val;
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_slice_enabled_fops,
+ i915_slice_enabled_get, i915_slice_enabled_set,
+ "%llu\n");
+
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
static const struct i915_debugfs_files {
@@ -4839,7 +4874,8 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
{"i915_dp_test_type", &i915_displayport_test_type_fops},
{"i915_dp_test_active", &i915_displayport_test_active_fops},
{"i915_guc_log_control", &i915_guc_log_control_fops},
- {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
+ {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
+ {"i915_slice_enabled", &i915_slice_enabled_fops}
};
int i915_debugfs_register(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bb6fc1e..7455d43 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -852,6 +852,7 @@ struct sseu_dev_info {
u8 has_slice_pg:1;
u8 has_subslice_pg:1;
u8 has_eu_pg:1;
+ u8 slice_enabled;
};
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 7d01dfe..2eee76b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -412,6 +412,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
gen9_sseu_info_init(dev_priv);
info->has_snoop = !info->has_llc;
+ info->sseu.slice_enabled = hweight8(info->sseu.slice_mask);
DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..2a1b641 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1743,7 +1743,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
*/
if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
- rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
+ rpcs |= INTEL_INFO(dev_priv)->sseu.slice_enabled <<
GEN8_RPCS_S_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
--
1.8.3.1
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