On Mon, Mar 27, 2017 at 02:30:08PM +0100, Chris Wilson wrote: > On Mon, Mar 27, 2017 at 04:19:58PM +0300, Mika Kuoppala wrote: > > Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > > > > > On Mon, Mar 27, 2017 at 01:12:30PM +0300, Mika Kuoppala wrote: > > >> Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > > >> > > >> > One POSTING_READ of ACTHD may not be enough to ensure that the seqno > > >> > write has been posted from the GPU and is now visible. So do three! > > >> > > > >> > > >> Is this about posting read triggering or just adding enough delay > > >> that the write gets through? > > > > > > It's purely about a delay that we guess will cover 99.9999% of cases. > > > > Acked-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > > Thanks, for checking over the idea. I'm going to apply it to > topic/core-for-CI for some extended soak testing and see if that > silences fi-snb-2600 Second run and the miss came back. Boo. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
