One POSTING_READ of ACTHD may not be enough to ensure that the seqno write has been posted from the GPU and is now visible. So do three! References: https://bugs.freedesktop.org/show_bug.cgi?id=97557 References: https://bugs.freedesktop.org/show_bug.cgi?id=100007 References: https://bugs.freedesktop.org/show_bug.cgi?id=100052 Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ab5e2e0623b7..2b5cd6039a6e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -766,6 +766,7 @@ static void gen6_seqno_barrier(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; + int loop; /* Workaround to force correct ordering between irq and seqno writes on * ivb (and maybe also on snb) by reading from a CS register (like @@ -783,7 +784,8 @@ gen6_seqno_barrier(struct intel_engine_cs *engine) * take the spinlock to guard against concurrent cacheline access. */ spin_lock_irq(&dev_priv->uncore.lock); - POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); + for (loop = 0; loop < 3; loop++) + POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); spin_unlock_irq(&dev_priv->uncore.lock); } -- 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
