On Thu, Feb 23, 2017 at 07:35:07PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Rather than sprinkling ideas of how big the DDI buf translation tables
> are somewhere in intel_dp.c, let's concentrate it all in intel_ddi.c
> where the actual tables are defined. To that end we introduce
> intel_ddi_dp_voltage_max() which will actually look at the proper
> translation table to determine what is the maximum voltage swing level
> supported.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: David Weinehall <david.weinehall@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++++++++
> drivers/gpu/drm/i915/intel_dp.c | 5 ++---
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6f8e57f127e5..0c3665f9e4f4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1615,6 +1615,24 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
> ddi_translations[level].deemphasis);
> }
>
> +u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + int n_entries;
> +
> + if (encoder->type == INTEL_OUTPUT_EDP)
> + intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
> + else
> + intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
> +
> + if (WARN_ON(n_entries < 1))
> + n_entries = 1;
> + if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
> + n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
> +
> + return index_to_dp_signal_levels[n_entries - 1];
> +}
> +
> static uint32_t translate_signal_level(int signal_levels)
> {
> int i;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 024798a9c016..e72c92a08c81 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3098,9 +3098,8 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> if (IS_GEN9_LP(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (INTEL_GEN(dev_priv) >= 9) {
> - if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> - return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> - return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + return intel_ddi_dp_voltage_max(encoder);
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (IS_GEN7(dev_priv) && port == PORT_A)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3c8aaca947d3..e9a90dcd15df 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1233,6 +1233,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
> uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> +u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
> +
> unsigned int intel_fb_align_height(struct drm_i915_private *dev_priv,
> unsigned int height,
> uint32_t pixel_format,
> --
> 2.10.2
>
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