Hi Jani, Thanks for this patch series. This definitely makes use of lane count and link rate cleaner while handling the link failures. I have tested these patches with compliance device along with my pending DRM link-status patches and it does the fallback as expected. It does not solve the problem of max link rate/lane count getting reset through ->detect callback from fill_modes(), but that will be fixed in a separate patch. As far as these patches, the fallback and compliance works properly: Tested-by: Manasi Navare <manasi.d.navare@xxxxxxxxx> Manasi On Fri, Feb 03, 2017 at 04:19:23PM +0200, Jani Nikula wrote: > v2 of [1], rebased and review addressed. > > BR, > Jani. > > > [1] http://mid.mail-archive.com/cover.1485459621.git.jani.nikula@xxxxxxxxx > > > Jani Nikula (13): > drm/i915/dp: use known correct array size in rate_to_index > drm/i915/dp: return errors from rate_to_index() > drm/i915/dp: rename rate_to_index() to intel_dp_rate_index() and reuse > drm/i915/dp: cache source rates at init > drm/i915/dp: generate and cache sink rate array for all DP, not just > eDP 1.4 > drm/i915/dp: use the sink rates array for max sink rates > drm/i915/dp: cache common rates with sink rates > drm/i915/dp: do not limit rate seek when not needed > drm/i915/dp: don't call the link parameters sink parameters > drm/i915/dp: add functions for max common link rate and lane count > drm/i915/mst: use max link not sink lane count > drm/i915/dp: localize link rate index variable more > drm/i915/dp: use readb and writeb calls for single byte DPCD access > > drivers/gpu/drm/i915/intel_dp.c | 284 ++++++++++++++------------ > drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +- > drivers/gpu/drm/i915/intel_dp_mst.c | 4 +- > drivers/gpu/drm/i915/intel_drv.h | 20 +- > 4 files changed, 173 insertions(+), 138 deletions(-) > > -- > 2.1.4 > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
