v2 of [1], rebased and review addressed. BR, Jani. [1] http://mid.mail-archive.com/cover.1485459621.git.jani.nikula@xxxxxxxxx Jani Nikula (13): drm/i915/dp: use known correct array size in rate_to_index drm/i915/dp: return errors from rate_to_index() drm/i915/dp: rename rate_to_index() to intel_dp_rate_index() and reuse drm/i915/dp: cache source rates at init drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4 drm/i915/dp: use the sink rates array for max sink rates drm/i915/dp: cache common rates with sink rates drm/i915/dp: do not limit rate seek when not needed drm/i915/dp: don't call the link parameters sink parameters drm/i915/dp: add functions for max common link rate and lane count drm/i915/mst: use max link not sink lane count drm/i915/dp: localize link rate index variable more drm/i915/dp: use readb and writeb calls for single byte DPCD access drivers/gpu/drm/i915/intel_dp.c | 284 ++++++++++++++------------ drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +- drivers/gpu/drm/i915/intel_dp_mst.c | 4 +- drivers/gpu/drm/i915/intel_drv.h | 20 +- 4 files changed, 173 insertions(+), 138 deletions(-) -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
