On Mon, Feb 6, 2017 at 12:59 PM, Daniel Vetter <daniel@xxxxxxxx> wrote: > On Mon, Feb 06, 2017 at 10:39:28AM -0700, Jordan Crouse wrote: >> This series of patches implements multiple ringbuffers and preemption for Adreno >> A5XX targets. Preemption allows a command to be interrupted at specific >> preemption points and execution switched to a different ringbuffer. >> >> The software alogrithm uses preemption to enforce quality of service for >> priority levels - commands to a certain ring preempt the rings of lower >> priority. Note that priority is a software construct; the driver chooses a ring >> to switch to and the hardware executes. This is important because it shows that >> preemption can be used for things other than priority (timeslices for quality of >> service for example). >> >> This initial series implements 4 ringbuffers to give sufficient coverage for the >> range of priority levels requested by the GLES and compute extensions. The >> targeted ringbuffer is specified in the command submission flags. The default >> ring is 0 (lowest priority). > > Link to userspace part that implements these extensions? Also which > gles/compute extensions are you talking about? Asking not just because of > the open source userspace requirement, but also because we want to > upstream a scheduler on the i915 side. Getting alignment on that across > drm drivers would be sweet. FWIW, we have had a GPU scheduler in amdgpu for several years now. We purposely tried to keep it largely separate from our driver so others could leverage it if they wanted to. See drivers/gpu/drm/amd/scheduler in the kernel. Alex > > Adding intel-gfx, I'll poke the folks working on this too. > -Daniel > >> >> Jordan >> >> Jordan Crouse (11): >> drm/msm: Make sure to detach the MMU during GPU cleanup >> drm/msm: Improve the zap shader >> drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA >> drm/msm: Remove idle function hook >> drm/msm: get an iova from the address space instead of an id >> drm/msm: Add a struct to pass configuration to msm_gpu_init() >> drm/msm: Remove memptrs->wptr >> drm/msm: Support multiple ringbuffers >> drm/msm: Shadow current pointer in the ring until command is complete >> drm/msm: Make the value of RB_CNTL (almost) generic >> drm/msm: Implement preemption for A5XX targets >> >> drivers/gpu/drm/msm/Makefile | 1 + >> drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 13 +- >> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 13 +- >> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 278 +++++++++++++++++----- >> drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 106 +++++++++ >> drivers/gpu/drm/msm/adreno/a5xx_power.c | 11 +- >> drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 367 ++++++++++++++++++++++++++++++ >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 215 +++++++++++------ >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 42 ++-- >> drivers/gpu/drm/msm/dsi/dsi_host.c | 15 +- >> drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 8 +- >> drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 18 +- >> drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 3 - >> drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 13 +- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 5 +- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 11 +- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 4 - >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 13 +- >> drivers/gpu/drm/msm/msm_drv.c | 43 ++-- >> drivers/gpu/drm/msm/msm_drv.h | 27 ++- >> drivers/gpu/drm/msm/msm_fb.c | 15 +- >> drivers/gpu/drm/msm/msm_fbdev.c | 10 +- >> drivers/gpu/drm/msm/msm_fence.c | 85 +++++-- >> drivers/gpu/drm/msm/msm_fence.h | 13 +- >> drivers/gpu/drm/msm/msm_gem.c | 124 +++++++--- >> drivers/gpu/drm/msm/msm_gem.h | 5 +- >> drivers/gpu/drm/msm/msm_gem_submit.c | 14 +- >> drivers/gpu/drm/msm/msm_gpu.c | 140 +++++++----- >> drivers/gpu/drm/msm/msm_gpu.h | 54 ++++- >> drivers/gpu/drm/msm/msm_kms.h | 3 + >> drivers/gpu/drm/msm/msm_ringbuffer.c | 14 +- >> drivers/gpu/drm/msm/msm_ringbuffer.h | 21 +- >> include/uapi/drm/msm_drm.h | 9 +- >> 33 files changed, 1324 insertions(+), 389 deletions(-) >> create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_preempt.c >> >> -- >> 1.9.1 >> >> _______________________________________________ >> dri-devel mailing list >> dri-devel@xxxxxxxxxxxxxxxxxxxxx >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > _______________________________________________ > dri-devel mailing list > dri-devel@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/dri-devel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
