On Mon, Feb 06, 2017 at 07:03:39PM +0800, Zhi Wang wrote: > Thanks for the merging. I guess that with your patches of keeping PD > structure under aliasing PPGTT mode in 32bit page table, the amount > of PDPs will not change anymore under aliasing PPGTT mode. :P Yes. That's the idea atm, we will preallocate the aliasing table and then keep the tree intact. The only disadvantage with gen8+ aliasing mode (compared to gen6) will be that we still have to walk the va range to pin the tree so that when we call clear_range afterwards we don't reap. The benefit from my pov, is that the special case for aliasing_ppgtt is within the aliasing_ppgtt code and not in the common code (which should be optimised for full-ppgtt as that is the default/typical use). -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
