Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
> After resetting, show the requests that each engine restarts from in the
> debug log.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ad55564350b4..39a4eaadd0a7 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1257,6 +1257,11 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> return ret;
> }
>
> +static u32 port_seqno(struct execlist_port *port)
> +{
> + return port->request ? port->request->global_seqno : 0;
> +}
> +
> static int gen8_init_common_ring(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *dev_priv = engine->i915;
> @@ -1282,6 +1287,10 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
> /* After a GPU reset, we may have requests to replay */
> clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
> if (!i915.enable_guc_submission && !execlists_elsp_idle(engine)) {
> + DRM_DEBUG_DRIVER("Restarting %s from requests [0x%x, 0x%x]\n",
> + engine->name,
> + port_seqno(&engine->execlist_port[0]),
> + port_seqno(&engine->execlist_port[1]));
> engine->execlist_port[0].count = 0;
> engine->execlist_port[1].count = 0;
> execlists_submit_ports(engine);
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
