From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Use a local variable for storing the request and engine
and at the same time drop the engine field from
i915_execbuffer_params since it is available from the
request.
text data bss dec hex filename
1085402 26398 2628 1114428 11013c i915.ko.0
1085354 26398 2628 1114380 11010c i915.ko.1
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 35 +++++++++++++++---------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 2991751516f8..119322eb9897 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -53,7 +53,6 @@ struct i915_execbuffer_params {
struct i915_vma *batch;
u32 dispatch_flags;
u32 batch_start;
- struct intel_engine_cs *engine;
struct drm_i915_gem_request *request;
};
@@ -1410,17 +1409,19 @@ execbuf_submit(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
struct list_head *vmas)
{
- struct drm_i915_private *dev_priv = params->request->i915;
+ struct drm_i915_gem_request *req = params->request;
+ struct drm_i915_private *dev_priv = req->i915;
+ struct intel_engine_cs *engine = req->engine;
u64 exec_start, exec_len;
int instp_mode;
u32 instp_mask;
int ret;
- ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
+ ret = i915_gem_execbuffer_move_to_gpu(req, vmas);
if (ret)
return ret;
- ret = i915_switch_context(params->request);
+ ret = i915_switch_context(req);
if (ret)
return ret;
@@ -1430,25 +1431,25 @@ execbuf_submit(struct i915_execbuffer_params *params,
case I915_EXEC_CONSTANTS_REL_GENERAL:
case I915_EXEC_CONSTANTS_ABSOLUTE:
case I915_EXEC_CONSTANTS_REL_SURFACE:
- if (instp_mode != 0 && params->engine->id != RCS) {
+ if (instp_mode != 0 && engine->id != RCS) {
DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
return -EINVAL;
}
if (instp_mode != dev_priv->relative_constants_mode) {
- if (INTEL_INFO(dev_priv)->gen < 4) {
+ if (INTEL_GEN(dev_priv) < 4) {
DRM_DEBUG("no rel constants on pre-gen4\n");
return -EINVAL;
}
- if (INTEL_INFO(dev_priv)->gen > 5 &&
+ if (INTEL_GEN(dev_priv) > 5 &&
instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
return -EINVAL;
}
/* The HW changed the meaning on this bit on gen6 */
- if (INTEL_INFO(dev_priv)->gen >= 6)
+ if (INTEL_GEN(dev_priv) >= 6)
instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
}
break;
@@ -1457,11 +1458,11 @@ execbuf_submit(struct i915_execbuffer_params *params,
return -EINVAL;
}
- if (params->engine->id == RCS &&
+ if (engine->id == RCS &&
instp_mode != dev_priv->relative_constants_mode) {
- struct intel_ring *ring = params->request->ring;
+ struct intel_ring *ring = req->ring;
- ret = intel_ring_begin(params->request, 4);
+ ret = intel_ring_begin(req, 4);
if (ret)
return ret;
@@ -1475,7 +1476,7 @@ execbuf_submit(struct i915_execbuffer_params *params,
}
if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
- ret = i915_reset_gen7_sol_offsets(params->request);
+ ret = i915_reset_gen7_sol_offsets(req);
if (ret)
return ret;
}
@@ -1486,15 +1487,14 @@ execbuf_submit(struct i915_execbuffer_params *params,
if (exec_len == 0)
exec_len = params->batch->size - params->batch_start;
- ret = params->engine->emit_bb_start(params->request,
- exec_start, exec_len,
- params->dispatch_flags);
+ ret = engine->emit_bb_start(req, exec_start, exec_len,
+ params->dispatch_flags);
if (ret)
return ret;
- trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
+ trace_i915_gem_ring_dispatch(req, params->dispatch_flags);
- i915_gem_execbuffer_move_to_active(vmas, params->request);
+ i915_gem_execbuffer_move_to_active(vmas, req);
return 0;
}
@@ -1831,7 +1831,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
* kept around beyond the duration of the IOCTL once the GPU
* scheduler arrives.
*/
- params.engine = engine;
params.dispatch_flags = dispatch_flags;
params.batch = batch;
params.batch_start = batch_start_offset;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
