On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira wrote:
> Information about which phy is dual channel is hardcoded in the phy init
> sequence. Split that to a separate struct so the init sequence is more
> generic.
>
> Signed-off-by: Ander Conselvan de Oliveira
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 +++--
> drivers/gpu/drm/i915/intel_dpio_phy.c | 63 +++++++++++++++++++++++++++++------
> 2 files changed, 60 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6d29fb..d3802c6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1308,8 +1308,13 @@ enum skl_disp_power_wells {
> #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
> _PORT_CL1CM_DW30_A)
>
> -/* Defined for PHY0 only */
> -#define BXT_PORT_CL2CM_DW6_BC _MMIO(0x6C358)
> +/* The spec defines this only for BXT PHY0, but lets assume that this
> + * would exist for PHY1 too if it had a second channel.
> + */
> +#define _PORT_CL2CM_DW6_A 0x162358
> +#define _PORT_CL2CM_DW6_BC 0x6C358
> +#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC, \
> + _PORT_CL2CM_DW6_A)
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> /* BXT PHY Ref registers */
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 2a18724..66d750a 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -114,6 +114,49 @@
> * -----------------
> */
>
> +/**
> + * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
> + */
> +struct bxt_ddi_phy_info {
> + /**
> + * @dual_channel: true if this phy has a second channel.
> + */
> + bool dual_channel;
> +
> + /**
> + * @channel: struct containing per channel information.
> + */
> + struct {
> + /**
> + * @port: which port maps to this channel.
> + */
> + enum port port;
> + } channel[2];
> +};
> +
> +static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
> + [DPIO_PHY0] = {
> + .dual_channel = true,
> +
> + .channel = {
> + [DPIO_CH0] = { .port = PORT_B },
> + [DPIO_CH1] = { .port = PORT_C },
> + }
> + },
> + [DPIO_PHY1] = {
> + .dual_channel = false,
> +
> + .channel = {
> + [DPIO_CH0] = { .port = PORT_A },
> + }
> + },
> +};
> +
> +{
Missing part above, got mangled into the next patch.
> + return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
> + BIT(phy_info->channel[DPIO_CH0].port);
> +}
> +
> void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
> enum port port, u32 margin, u32 scale,
> u32 enable, u32 deemphasis)
> @@ -183,9 +226,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> return false;
> }
>
> - for_each_port_masked(port,
> - phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
> - BIT(PORT_A)) {
> + for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
> u32 tmp = I915_READ(BXT_PHY_CTL(port));
>
> if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
> @@ -220,6 +261,7 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
>
> void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> {
> + const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
> u32 val;
>
> if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
> @@ -272,10 +314,10 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> SUS_CLK_CONFIG;
> I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
>
> - if (phy == DPIO_PHY0) {
> - val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
> + if (phy_info->dual_channel) {
> + val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
> val |= DW6_OLDO_DYN_PWR_DOWN_EN;
> - I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
> + I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
> }
>
> val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> @@ -290,7 +332,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> * FIXME: Clarify programming of the following, the register is
> * read-only with bit 6 fixed at 0 at least in stepping A.
> */
> - if (phy == DPIO_PHY1)
> + if (!phy_info->dual_channel)
> val |= OCL2_LDOFUSE_PWR_DIS;
> I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
>
> @@ -363,6 +405,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
> enum dpio_phy phy)
> {
> + const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
> uint32_t mask;
> bool ok;
>
> @@ -388,10 +431,10 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
> ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
> "BXT_PORT_CL1CM_DW28(%d)", phy);
>
> - if (phy == DPIO_PHY0)
> - ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
> + if (phy_info->dual_channel)
> + ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
> DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
> - "BXT_PORT_CL2CM_DW6_BC");
> + "BXT_PORT_CL2CM_DW6(%d)", phy);
>
> /*
> * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
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