On Thu, Sep 29, 2016 at 04:35:55PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
>
> Also verify the order at runtime. This was we can start using
> binary search on it in a following patch.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 28 ++++++++++++++++++++++------
> 1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 893d73c7368a..8f25cd7ab50f 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -657,15 +657,29 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
> })
>
> static const i915_reg_t gen8_shadowed_regs[] = {
> - GEN6_RPNSWREQ,
> - GEN6_RC_VIDEO_FREQ,
> - RING_TAIL(RENDER_RING_BASE),
> - RING_TAIL(GEN6_BSD_RING_BASE),
> - RING_TAIL(VEBOX_RING_BASE),
> - RING_TAIL(BLT_RING_BASE),
> + RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
> + GEN6_RPNSWREQ, /* 0xA008 */
> + GEN6_RC_VIDEO_FREQ, /* 0xA00C */
> + RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */
> + RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */
> + RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
> /* TODO: Other registers are not yet used */
> };
Ok.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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