Driver needs to ensure that it doesn't mask the PM interrupts, which are
unmasked/needed by GuC firmware. For that, Driver maintains a bitmask of
interrupts to be kept enabled, pm_intr_keep.
By default, RP Up/Down Threshold Interrupt bits (and others) in
GEN6_PMINTRMSK register were unmasked (by BIOS) before GuC Load. Hence
Driver was keeping them unmasked always assuming GuC needed them.
As an optimization, Driver needs to mask these bits in order to
avoid redundant UP threshold interrupts when frequency is set to maximum,
RP0 or Down threshold interrupts when frequency is set to minimum, RPn.
This patch will mask all bits in GEN6_PMINTRMSK before GuC is loaded to
ensure pm_intr_keep reflects only interrupts that are needed by GuC. Post
GuC load, writing cur_freq will restore bits other than pm_intr_keep.
v2: No functional change. Moving the sanitization of PMINTRMSK inside
intel_guc_setup. Should take care of scenarios where standalone guc
setup is done like deferred load in Android. (Sagar)
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Szwichtenberg, Radoslaw <radoslaw.szwichtenberg@xxxxxxxxx>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 13 +++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 2 +-
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4bfb01c..431c17d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1734,6 +1734,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
+u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val);
void gen6_rps_busy(struct drm_i915_private *dev_priv);
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
void gen6_rps_idle(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 7ace96b..061d917 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -483,6 +483,12 @@ int intel_guc_setup(struct drm_device *dev)
guc_interrupts_release(dev_priv);
+ /*
+ * Mask all interrupts to know which interrupts are needed by GuC.
+ * Restore host side interrupt masks post load.
+ */
+ I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
+
guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
@@ -532,6 +538,13 @@ int intel_guc_setup(struct drm_device *dev)
guc_interrupts_capture(dev_priv);
}
+ /*
+ * Below write will ensure mask for RPS interrupts is restored back
+ * w.r.t cur_freq, particularly post reset.
+ */
+ I915_WRITE(GEN6_PMINTRMSK,
+ gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
+
return 0;
fail:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 57ded11..7c88acfa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4878,7 +4878,7 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
dev_priv->rps.last_adj = 0;
}
-static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
+u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
{
u32 mask = 0;
--
1.9.1
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