On ma, 2016-08-01 at 10:11 +0100, Chris Wilson wrote:
> For consistency, internal functions should take drm_i915_private rather
> than drm_device. Now that we are subclassing drm_device, there are no
> more size wins, but being consistent is its own blessing.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +++--
> drivers/gpu/drm/i915/i915_gem.c | 30 ++++++++++++++++--------------
> drivers/gpu/drm/i915/i915_gem_tiling.c | 8 ++++----
> 3 files changed, 23 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b6e56ecb8637..3d73394b52d7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3241,8 +3241,9 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
> int i915_gem_open(struct drm_device *dev, struct drm_file *file);
> void i915_gem_release(struct drm_device *dev, struct drm_file *file);
>
> -u64 i915_gem_get_ggtt_size(struct drm_device *dev, u64 size, int tiling_mode);
> -u64 i915_gem_get_ggtt_alignment(struct drm_device *dev, u64 size,
> +u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
> + int tiling_mode);
> +u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
> int tiling_mode, bool fenced);
>
> int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 432868eafa60..f11bf6c4f86a 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1846,25 +1846,26 @@ i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
>
> /**
> * i915_gem_get_ggtt_size - return required global GTT size for an object
> - * @dev: drm device
> + * @dev_priv: i915 device
> * @size: object size
> * @tiling_mode: tiling mode
> *
> * Return the required GTT size for an object, taking into account
> * potential fence register mapping.
> */
> -u64 i915_gem_get_ggtt_size(struct drm_device *dev, u64 size, int tiling_mode)
> +u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
> + u64 size, int tiling_mode)
> {
> u64 ggtt_size;
>
> GEM_BUG_ON(size == 0);
>
> - if (INTEL_GEN(dev) >= 4 ||
> + if (INTEL_GEN(dev_priv) >= 4 ||
> tiling_mode == I915_TILING_NONE)
> return size;
>
> /* Previous chips need a power-of-two fence region when tiling */
> - if (IS_GEN3(dev))
> + if (IS_GEN3(dev_priv))
> ggtt_size = 1024*1024;
> else
> ggtt_size = 512*1024;
> @@ -1877,7 +1878,7 @@ u64 i915_gem_get_ggtt_size(struct drm_device *dev, u64 size, int tiling_mode)
>
> /**
> * i915_gem_get_ggtt_alignment - return required GTT alignment for an object
> - * @dev: drm device
> + * @dev_priv: i915 device
> * @size: object size
> * @tiling_mode: tiling mode
> * @fenced: is fenced alignemned required or not
> @@ -1885,7 +1886,7 @@ u64 i915_gem_get_ggtt_size(struct drm_device *dev, u64 size, int tiling_mode)
> * Return the required GTT alignment for an object, taking into account
> * potential fence register mapping.
> */
> -u64 i915_gem_get_ggtt_alignment(struct drm_device *dev, u64 size,
> +u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
> int tiling_mode, bool fenced)
> {
> GEM_BUG_ON(size == 0);
> @@ -1894,7 +1895,7 @@ u64 i915_gem_get_ggtt_alignment(struct drm_device *dev, u64 size,
> * Minimum alignment is 4k (GTT page size), but might be greater
> * if a fence register is needed for the object.
> */
> - if (INTEL_GEN(dev) >= 4 || (!fenced && IS_G33(dev)) ||
> + if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) ||
> tiling_mode == I915_TILING_NONE)
> return 4096;
>
> @@ -1902,7 +1903,7 @@ u64 i915_gem_get_ggtt_alignment(struct drm_device *dev, u64 size,
> * Previous chips need to be aligned to the size of the smallest
> * fence register that can contain the object.
> */
> - return i915_gem_get_ggtt_size(dev, size, tiling_mode);
> + return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode);
> }
>
> static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
> @@ -2991,14 +2992,14 @@ i915_gem_object_insert_into_vm(struct drm_i915_gem_object *obj,
>
> view_size = i915_ggtt_view_size(obj, ggtt_view);
>
> - fence_size = i915_gem_get_ggtt_size(dev,
> + fence_size = i915_gem_get_ggtt_size(dev_priv,
> view_size,
> obj->tiling_mode);
> - fence_alignment = i915_gem_get_ggtt_alignment(dev,
> + fence_alignment = i915_gem_get_ggtt_alignment(dev_priv,
> view_size,
> obj->tiling_mode,
> true);
> - unfenced_alignment = i915_gem_get_ggtt_alignment(dev,
> + unfenced_alignment = i915_gem_get_ggtt_alignment(dev_priv,
> view_size,
> obj->tiling_mode,
> false);
> @@ -3702,13 +3703,14 @@ i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
> {
> struct drm_i915_gem_object *obj = vma->obj;
> + struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
> bool mappable, fenceable;
> u32 fence_size, fence_alignment;
>
> - fence_size = i915_gem_get_ggtt_size(obj->base.dev,
> + fence_size = i915_gem_get_ggtt_size(dev_priv,
> obj->base.size,
> obj->tiling_mode);
> - fence_alignment = i915_gem_get_ggtt_alignment(obj->base.dev,
> + fence_alignment = i915_gem_get_ggtt_alignment(dev_priv,
> obj->base.size,
> obj->tiling_mode,
> true);
> @@ -3717,7 +3719,7 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
> (vma->node.start & (fence_alignment - 1)) == 0);
>
> mappable = (vma->node.start + fence_size <=
> - to_i915(obj->base.dev)->ggtt.mappable_end);
> + dev_priv->ggtt.mappable_end);
>
> obj->map_and_fenceable = mappable && fenceable;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index 4e42da691e4e..b7f9875f69b4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -117,15 +117,16 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> static bool
> i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
> {
> + struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
> u32 size;
>
> if (tiling_mode == I915_TILING_NONE)
> return true;
>
> - if (INTEL_INFO(obj->base.dev)->gen >= 4)
> + if (INTEL_GEN(dev_priv) >= 4)
> return true;
>
> - if (IS_GEN3(obj->base.dev)) {
> + if (IS_GEN3(dev_priv)) {
> if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
> return false;
> } else {
> @@ -133,8 +134,7 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
> return false;
> }
>
> - size = i915_gem_get_ggtt_size(obj->base.dev,
> - obj->base.size, tiling_mode);
> + size = i915_gem_get_ggtt_size(dev_priv, obj->base.size, tiling_mode);
> if (i915_gem_obj_ggtt_size(obj) != size)
> return false;
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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