On Thu, Jul 28, 2016 at 12:12:32PM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform definition allows for
> - standard place when adding new features from new platforms
> - possible to see supported features when dumping struct
> definitions
>
> Signed-off-by: Carlos Santa <carlos.santa@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> drivers/gpu/drm/i915/i915_pci.c | 4 ++++
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 41283c5..510bab6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -782,6 +782,7 @@ struct intel_csr {
> func(has_dp_mst) sep \
> func(has_aux_irq) sep \
> func(has_gmbus_irq) sep \
> + func(has_fw_blc) sep \
> func(has_pipe_cxsr) sep \
> func(has_hotplug) sep \
> func(cursor_needs_physical) sep \
> @@ -2733,7 +2734,7 @@ struct drm_i915_cmd_table {
> #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
> #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
>
> -#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
> +#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->has_fw_blc)
> #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
> #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 7a14f68..0df6911 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -85,6 +85,7 @@ static const struct intel_device_info intel_i865g_info = {
>
> #define GEN3_FEATURES \
> .gen = 3, .num_pipes = 2, \
> + .has_fw_blc = 1, \
> .ring_mask = RENDER_RING, \
> GEN_DEFAULT_PIPEOFFSETS, \
> CURSOR_OFFSETS
> @@ -170,6 +171,7 @@ static const struct intel_device_info intel_pineview_info = {
> .need_gfx_hws = 1, .has_hotplug = 1, \
> .has_aux_irq = 1, \
> .has_gmbus_irq = 1, \
> + .has_fw_blc = 1, \
> .ring_mask = RENDER_RING | BSD_RING, \
> GEN_DEFAULT_PIPEOFFSETS, \
> CURSOR_OFFSETS
> @@ -235,6 +237,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
> .has_rc6 = 1, \
> .has_aux_irq = 1, \
> .has_gmbus_irq = 1, \
> + .has_fw_blc = 1, \
> .need_gfx_hws = 1, .has_hotplug = 1, \
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
> .display_mmio_offset = VLV_DISPLAY_BASE, \
> @@ -315,6 +318,7 @@ static const struct intel_device_info intel_cherryview_info = {
> .has_rc6 = 1,
> .has_aux_irq = 1,
> .has_gmbus_irq = 1,
> + .has_fw_blc = 1,
This patch is mosly bogus. HAS_FW_BLC should only be true for gen3, and
it should actually be called HAS_FW_BLC_SELF. Probably easiest to just
replace the only place it's used with IS_GEN3.
Hmm. That code looks partially bogus anyway. It forgets to program
FW_BLC_SELF on 915G. Looks like the spec is confusing too. The register
supposedly exits there, but there isn't a memory SR enable bit to found
anywhere for 915G. Unfortunately I don't have the hardware to find out
what's going on with that, so can't really fix it. Oh and it also fails
to handle the 945G/GM cpp=4 workaround. I guess I'll have to send a patch
for that at least...
> .display_mmio_offset = VLV_DISPLAY_BASE,
> GEN_CHV_PIPEOFFSETS,
> CURSOR_OFFSETS,
> --
> 1.9.1
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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--
Ville Syrjälä
Intel OTC
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