On 20/02/2021 12:59, Nick Hilliard
wrote:
Hi Gorry,
Gorry Fairhurst via Datatracker wrote on 18/02/2021 16:54:
* I suggest a more powerful chip design might not have reduced performance, but
would cost more: /but the overall performance of the system will be reduced. /
- so maybe either performance is reduced or the system cost increased?
The practical issue here is that on all hardware, if you increase the complexity of a pipeline, the performance will be reduced. This is a statement of what happens in the real world on installed systems.
The purpose of this ID was to provide an practical overview of the real-world problems that operators are likely to experience, and why they happen, rather than getting into the thornier issue of analysing the what-ifs and wherefores of design choices. So we deliberately steered clear of value judgements, including the trade-offs between cost, complexity and performance - there's too much scope in there to get lost in the long grass.
Nick
Yes, I thought that was the intention, although the current text seems to me to be describing a tradeoff, and the word "cost" is ambiguous in terms of processing resource and manufacture cost, so I agree we could do better. The current text says:
Technical constraints mean that there is a trade-off between the amount of data sent to the lookup engine and the overall performance of the lookup engine. If more data is sent, the lookup engine can inspect further into the packet, but the overall performance of the system will be reduced. If less data is sent, the overall performance of the router will be increased but the packet lookup engine may not be able to inspect far enough into a packet to determine how it should be handled. - Maybe "overall performance" isn't the right word here either. You will know what is best - perhaps this is talking about "packet forwrading rate"? Best wishes, Gorry
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