Hi guys, Thanks for all your discussions. I believe its very informative, but I don't think I can follow your suggestions. I'm not a software programmer, nor a part of the compiler design team. Your jargon and majority of asm constraint wordage in the GCC manual remains unclear for me. I'm just a GCC user, which wants to use new CPU instructions with old compiler version. I have no any intention to modify GCC by myself. Regards Alex. -----Original Message----- From: Ian Lance Taylor [mailto:iant@xxxxxxxxxx] Sent: Saturday, February 09, 2013 9:54 PM To: Chung-Ju Wu Cc: Georg-Johann Lay; Grobman Alexander-R53196; gcc-help@xxxxxxxxxxx Subject: Re: builtin assembler constraints On Sat, Feb 9, 2013 at 6:28 PM, Chung-Ju Wu <jasonwucj@xxxxxxxxx> wrote: > > I guess Georg refers to this situation: > > EVEN_SET_REGISTERS: $r0, $r2, $r4, $r6, ... > ODD_SET_REGISTERS: $r1, $r3, $r5, $r7, ... > > And IRA/reload cannot allocate $r0+$r2 for DImode/DFmode. > Because a reg rtx with a machine mode that specifies more than one > word actually represents several consecutive hardware registers. For that kind of thing you use HARD_REGNO_MODE_OK to say that DImode/DFmode can only go in even registers. Then you make the insns use the class that permits all registers. That does not prevent you from also having even and odd register classes. Ian
