On Sat, Feb 9, 2013 at 6:28 PM, Chung-Ju Wu <jasonwucj@xxxxxxxxx> wrote: > > I guess Georg refers to this situation: > > EVEN_SET_REGISTERS: $r0, $r2, $r4, $r6, ... > ODD_SET_REGISTERS: $r1, $r3, $r5, $r7, ... > > And IRA/reload cannot allocate $r0+$r2 for DImode/DFmode. > Because a reg rtx with a machine mode that specifies more than > one word actually represents several consecutive hardware registers. For that kind of thing you use HARD_REGNO_MODE_OK to say that DImode/DFmode can only go in even registers. Then you make the insns use the class that permits all registers. That does not prevent you from also having even and odd register classes. Ian
