Hi,
>> Show us the RTL and the define_peephole2.
Thanks for looking at the issue.
Please find attached the file tbit.txt which has complete information
of RTL pattern generated and defined peephole patterns.
>> From what you have described so far peep2_reg_dead_p ought to work.
To use far peep2_reg_dead_p; peephole2 patterns were defined.
far peep2_reg_dead_p masked the generation of tbit instruction completely.
Hence, tbit instructions were not at all generated in any instance.
>> Also, which version of gcc?
We are using gcc-4.5.1 version.
Thanks & Regards,
Naveen
RTL Pattern without the peephole optimization
============================================================================================================================================================
#(insn 13 36 14 /home/Src/Components/FWU/Manager/FwuManager.c:1245 (set (reg:HI 7 r7 [orig:26 Fdi[0].Flags ] [26])
# (mem/s:HI (symbol_ref:SI ("Fdi") [flags 0x2] <var_decl 0xb7a5b3f4 Fdi>) [3 Fdi[0].Flags+0 S2 A16])) 70 {*movhi_short} (expr_list:REG_EQUIV (mem/s:HI (symbol_ref:SI ("Fdi") [flags 0x2] <var_decl 0xb7a5b3f4 Fdi>) [3 Fdi[0].Flags+0 S2 A16])
# (nil)))
loadw _Fdi@l, r7 # Fdi[0].Flags, Fdi[0].Flags # 13 *movhi_short/5 [length = 6]
#(insn 14 13 15 /home/Src/Components/FWU/Manager/FwuManager.c:1245 (set (reg:HI 7 r7 [25])
# (and:HI (reg:HI 7 r7 [orig:26 Fdi[0].Flags ] [26])
# (const_int 16384 [0x4000]))) 27 {andhi3} (nil))
andw $16384, r7 #, tmp25 # 14 andhi3/3 [length = 4]
#(jump_insn 15 14 16 /home/Src/Components/FWU/Manager/FwuManager.c:1245 (parallel [
# (set (pc)
# (if_then_else (ne (reg:HI 7 r7 [25])
# (const_int 0 [0x0]))
# (label_ref:SI 27)
# (pc)))
# (clobber (cc0))
# ]) 74 {branchnehi} (expr_list:REG_BR_PROB (const_int 7100 [0x1bbc])
# (nil))
# -> 27)
bne0w r7,.L9 # tmp25, # 15 branchnehi [length = 2]
============================================================================================================================================================
RTL Pattern after the peephole optimization
===============================================================================================================
#(insn 205 258 27 /home/Src/Components/FWU/Manager/FwuManager.c:1803 (parallel [
# (reg:HI 2 r2 [54])
# (reg/v:HI 0 r0 [orig:23 f ] [23])
# (const_int 8 [0x8])
# (ne (reg:HI 2 r2 [54])
# (const_int 0 [0x0]))
# (code_label 163 253 164 70 "" [5 uses])
# ]) 147 {cr16_call_value+13} (nil))
tbit $3,r0 #, f # 205 cr16_call_value+13 [length = 2]
bfs .L70 #,
RTL Pattern
#(insn 17 16 18 /home/Src/Components/FWU/Manager/FwuManager.c:1249 (set (reg:HI 3 r3)
# (const_int 16383 [0x3fff])) 70 {*movhi_short} (nil))
movw $16383, r3 #, # 17 *movhi_short/3 [length = 4]
#(insn 18 17 19 /home/Src/Components/FWU/Manager/FwuManager.c:1249 (set (reg:QI 2 r2)
# (reg:QI 7 r7 [25])) 69 {*movqi_short} (expr_list:REG_EQUAL (const_int 0 [0x0])
# (nil)))
movb r7, r2 # tmp25, # 18 *movqi_short/1 [length = 2]
================================================================================================================
Peephole pattern used to generate the tbit instruction and hence optmized code
====================================================================================
(define_peephole
[(set (match_operand:CR16IM 0 "register_operand" "")
(match_operand:CR16IM 1 "memory_operand" ""))
(set (match_dup 0)
(and:CR16IM (match_dup 0)
(match_operand 2 "const_int_operand" "v")))
(parallel [(set (pc)
(if_then_else (match_operator 3 "ordered_comparison_operator"
[(match_dup 0)
(const_int 0)])
(label_ref (match_operand 4 "" ""))
(pc)))
(clobber (cc0))])]
"TARGET_BIT_OPS && satisfies_constraint_v (operands[2])"
"tbit%t0\t$%s2,%1\;bf%o3\t%l4")
Extra Info
Constarint v allows (1, 2 ......... -> 8192, 16384)
Print operand 't' prints b, w, w on QI, HI and SI mode respectively
Print operand 's' prints bit position
Print operand 'o' prints c on EQ and s on NE operations
====================================================================================
Peephole2 pattern used to generate tbit instruction using far peep2_reg_dead_p
====================================================================================
(define_peephole2
[(set (match_operand:CR16IM 0 "register_operand" "")
(match_operand:CR16IM 1 "memory_operand" ""))
(set (match_dup 0)
(and:CR16IM (match_dup 0)
(match_operand 2 "const_int_operand" "v")))
(parallel [(set (pc)
(if_then_else (match_operator 3 "ordered_comparison_operator"
[(match_dup 0)
(const_int 0)])
(label_ref (match_operand 4 "" ""))
(pc)))
(clobber (cc0))])]
"TARGET_BIT_OPS && satisfies_constraint_v (operands[2])
&& far peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 0)
(unspec [(match_dup 1)(match_dup 2)] UNSPEC_TBIT))
(set (match_dup 0)
(unspec [(match_operator 3 ""
[(match_dup 1)
(const_int 0)])
(label_ref (match_dup 4))
(match_dup 0)] UNSPEC_BRANCH))]
""
)
====================================================================================
UNSPEC instructions used in peephole2 patterns
====================================================================================
(define_insn "tbit"
[(set (match_operand 0 "" "")
(unspec [(match_operand 1 "" "m,i")(match_operand 2 "" "")] UNSPEC_TBIT))]
""
"@
tbit%t0\t$%s2,%1
tbit%t0\t$%s3,%c1"
[(set_attr "length" "2")]
)
(define_insn "branch_fs"
[(set (match_operand 0 "" "")
(unspec [(match_operator 1 ""
[(match_operand 2 "" "")
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(match_operand 4 "" "")] UNSPEC_BRANCH))]
""
"bf%o1\t%l3"
[(set_attr "length" "2")]
)
====================================================================================
The generated assembly in the erraneous function
===================================================================
Generated assembler:
14019 _DeviceDataInit:
14022 0000 1E01 push ra
14023 0002 0701 push $1, r7
14026 0004 935A movw $-1, r3 #,
14027 0006 0258 movb $0, r2 #,
14028 0008 00C00000 bal (ra), _ClrFlags@c #
14031 000c 1100E0F0 tbitw $14,_Fdi@l # Fdi[0].Flags,, Fdi[0].Flags
14031 0000
14032 0012 8010 bfs .L9 #,
14034 0014 B35AFF3F movw $16383, r3 #,
14035 0018 7259 movb r7, r2 # tmp25, --------> Problem here r7 used without initialization
14036 001a 00C00000 bal (ra), _ClrFlags@c #
14038 001e 135A movw $1, r3 #,
14039 0020 7259 movb r7, r2 # tmp25, --------> Problem here r7 used without initialization
14040 0022 00C00000 bal (ra), _SetFlags@c #
14045 0026 0702 pop $1, r7
14046 0028 1E03 popret ra
RTL of the above problem
================================================================================================================
#(insn 13 36 16 /home/Src/Components/FWU/Manager/FwuManager.c:1245 (parallel [
# (reg:HI 7 r7 [orig:26 Fdi[0].Flags ] [26])
# (mem/s:HI (symbol_ref:SI ("Fdi") [flags 0x2] <var_decl 0xb7a873f4 Fdi>) [3 Fdi[0].Flags+0 S2 A16])
# (const_int 16384 [0x4000])
# (ne (reg:HI 7 r7 [25])
# (const_int 0 [0x0]))
# (code_label 27 38 28 9 "" [1 uses])
# ]) 136 {cr16_call_value+2} (expr_list:REG_EQUIV (mem/s:HI (symbol_ref:SI ("Fdi") [flags 0x2] <var_decl 0xb7a873f4 Fdi>) [3 Fdi[0].Flags+0 S2 A16])
# (nil)))
tbitw $14,_Fdi@l # Fdi[0].Flags,, Fdi[0].Flags # 13 cr16_call_value+2 [length = 6]
bfs .L9 #,
.loc 1 1249 0
#(insn 17 16 18 /home/Src/Components/FWU/Manager/FwuManager.c:1249 (set (reg:HI 3 r3)
# (const_int 16383 [0x3fff])) 70 {*movhi_short} (nil))
movw $16383, r3 #, # 17 *movhi_short/3 [length = 4]
#(insn 18 17 19 /home/Src/Components/FWU/Manager/FwuManager.c:1249 (set (reg:QI 2 r2)
# (reg:QI 7 r7 [25])) 69 {*movqi_short} (expr_list:REG_EQUAL (const_int 0 [0x0])
# (nil)))
movb r7, r2 # tmp25, # 18 *movqi_short/1 [length = 2] --------> Problem here r7 used without initialization
================================================================================================================
