On 07/05/2011 12:49 PM, Sebastian Huber wrote:
> Hello,
>
> I use a NXP LPC2478 and I probably have a problem with its ARM7TDMI-S core.
> The following instruction will be not executed according to the specification
> (ARM Architecture Reference Manual, Issue I):
>
> stmia r3!, {r1-r3}
>
> The specification says (page A7-96):
>
> Finally, the base register <Rn> is incremented by 4 times the numbers of
> registers in <registers>.
>
> This means the original value of r3 should be written to memory. This is not
> the case. Instead the new value will be written to memory.
>
> Previous GCC versions (before 4.6) generated less optimal code and did not use
> a stmia here.
>
> Now my GCC question:
>
> I can prevent the stmia instruction if I use the -fno-peephole2 option.
> According to the command line help this disables "an RTL peephole pass before
> sched2". Do I loose a big potential for optimizations here?
>
> Have a nice day!
>
This is not a NXP LPC2478 problem! GCC 4.6.1 generates UNPREDICTABLE code.
According to the manual we have in "Operational restriction":
"If <Rn> is specified in <registers> and write back is specified:
- If <Rn> is the lowest-numbered register specified in <registers>, the
original value of <Rn> is stored
- Otherwise, the stored value of <Rn> is UNPREDICTABLE"
Since r3 is not the lowest-numbered register specified in {r1-r3} the stored
value of r3 is UNPREDICTABLE.
--
Sebastian Huber, embedded brains GmbH
Address : Obere Lagerstr. 30, D-82178 Puchheim, Germany
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E-Mail : sebastian.huber@xxxxxxxxxxxxxxxxxx
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