Boris Boesler writes: > Hi! > > > In my earlier message I explained what people do today for processors > > which need NOP instructions to be inserted. > > > > Nobody is working on implementing a better approach. > > I had a small discussion with Ian, which showed that my problem is > not understood. I try to summarize my previous emails: > > I have a processor with a 6 stages pipeline. Every stage is used > for exactly one cycle. This means: > 1) there can never be a hardware structural hazard (that's good) > 2) scheduling is not needed (even better) > > So what's the problem? The problem is that there are 2 stage which > can read registers and there is no bypass/result-forwarding from the > register-write-back to the first register-read-stage. > The following program is correct on my processor (pseudo-code): > A0 := &a > A0 := &b > NOP > A1 := 1; > A2 := (A0) + A1 ; contents of memory at label a plus 1 > A3 := (A0) + A1 ; contents of memory at label b plus 1 > > There has to be a number of instructions (e.g. NOPs) between > writing the address-register A0 and reading it for indirect memory- > access. To solve this I need scheduling. I implemented the scheduler > specification including its bypasses. The code is scheduled > correctly, as I can see in the verbose output. The missing/empty > cycles are visible - but empty. > > Now I need a pass to insert the missing NOPs. Is there some special reason you can't do this in machine dependent reorg? That seems like the obvious place. Just walk every basic block stuffing NOPs. Andrew. -- Red Hat UK Ltd, Amberley Place, 107-111 Peascod Street, Windsor, Berkshire, SL4 1TE, UK Registered in England and Wales No. 3798903
