Hi GCC:
I have a question about GCC compiler in MIPS CPU.
Following is function that include "switch ..case" statement,
#define VOS_OK (0)
typedef unsigned long VOS_UINT32;
VOS_UINT32 VOS_ShowDopraInfoEx( VOS_UINT32 ulFlag )
{
int x = ulFlag;
switch(x){
case 1:
vos_printf("para is 1\n");
break;
case 2:
vos_printf("para is 2\n");
break;
case 3:
vos_printf("para is 3\n");
break;
case 4:
vos_printf("para is 4\n");
break;
case 5:
vos_printf("para is 5\n");
break;
case 6:
vos_printf("para is 6\n");
break;
default:
vos_printf("para is default.\n");
break;
}
return VOS_OK;
}
I use GCC 2.96 in Tornado2.2 to compile it, following is assemble code dump from obj file,
addiu $a0,$a0,-1
addiu $sp,$sp,-40
sltiu $v0,$a0,6
beqz $v0,c0 <VOS_ShowDopraInfoEx+0xc0>
sd $ra,32($sp)
sll $v0,$a0,0x2
lui $v1,0x0
daddu $v1,$v1,$v0
lw $v1,120($v1)
jr $v1
lui $a0,0x0
jal 0 <VOS_ShowDopraInfoEx>
daddiu $a0,$a0,0
j d0 <VOS_ShowDopraInfoEx+0xd0>
ld $ra,32($sp)
nop
lui $a0,0x0
....
as we know, lw $v1,120($v1) will load word memory to register, and jr $v1 will do PC<-v1,
that is to say, memory will store address of instrution,
I think that GCC compiler write address of instrution to memory,
below is data section of obj file,
80180000: 7061 7261 2069 7320 310a 0000 0000 0000 *para is 1.......*
80180010: 7061 7261 2069 7320 320a 0000 0000 0000 *para is 2.......*
80180020: 7061 7261 2069 7320 330a 0000 0000 0000 *para is 3.......*
80180030: 7061 7261 2069 7320 340a 0000 0000 0000 *para is 4.......*
80180040: 7061 7261 2069 7320 350a 0000 0000 0000 *para is 5.......*
80180050: 7061 7261 2069 7320 360a 0000 0000 0000 *para is 6.......*
80180060: 7061 7261 2069 7320 6465 6661 756c 740a *para is default.*
80180070: 0000 0000 0000 0000 0000 0030 0000 0048 *...........0...H*
80180080: 0000 0060 0000 0078 0000 0090 0000 00a8 *...`...x........*
"0030 0000 0048 0000 0060 0000 0078 0000 0090 0000 00a8" is address of instrution, there have six instructions.
following is code and data section of program,
compare it to data seciton of obj, I find memory have been modified, from relative address to absolute address of instruction.
0x80e13870 2484ffff addiu a0,a0,65535
0x80e13874 27bdffd8 addiu sp,sp,65496
0x80e13878 2c820006 sltiu v0,a0,6
0x80e1387c 1040002c beqz v0,0x80e13930
0x80e13880 ffbf0020 sd ra,32(sp)
0x80e13884 00041080 sll v0,a0,2
0x80e13888 3c038124 lui v1,0x8124
0x80e1388c 0062182d daddu v1,v1,v0
0x80e13890 8c63a838 lw v1,43064(v1)
0x80e13894 00600008 jr v1
8123a7c0: 7061 7261 2069 7320 310a 0000 0000 0000 *para is 1.......*
8123a7d0: 7061 7261 2069 7320 320a 0000 0000 0000 *para is 2.......*
8123a7e0: 7061 7261 2069 7320 330a 0000 0000 0000 *para is 3.......*
8123a7f0: 7061 7261 2069 7320 340a 0000 0000 0000 *para is 4.......*
8123a800: 7061 7261 2069 7320 350a 0000 0000 0000 *para is 5.......*
8123a810: 7061 7261 2069 7320 360a 0000 0000 0000 *para is 6.......*
8123a820: 7061 7261 2069 7320 6465 6661 756c 740a *para is default.*
8123a830: 0000 0000 0000 0000 80e1 38a0 80e1 38b8 *..........8...8.*
8123a840: 80e1 38d0 80e1 38e8 80e1 3900 80e1 3918 *..8...8...9...9.*
My question is why Linker know how much address of instruction will be modified,
has obj file information about this or other?
thanks,
-Abel
