https://bugzilla.kernel.org/show_bug.cgi?id=91861 --- Comment #11 from Mike S. <michael.selig@xxxxxxxxx> --- Thanks for the info. It hasn't happened again so far. > ... you are driving the PLL so close to the edge ... Can you please explain what you mean? Are you saying that the higher fb_div & ref_div are pushing the PLL harder or faster? Please bear in mind that I am a programmer, not an electrical engineer, and though I do understand the basic principles of video displays (dot clocks, refresh rates, blanking etc), to me these dividers are just numbers used to set the dot clock. -- You are receiving this mail because: You are watching the assignee of the bug. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
