https://bugzilla.kernel.org/show_bug.cgi?id=91861 --- Comment #12 from Christian König <deathsimple@xxxxxxxxxxx> --- (In reply to Mike S. from comment #11) > Thanks for the info. It hasn't happened again so far. > > > ... you are driving the PLL so close to the edge ... > Can you please explain what you mean? Are you saying that the higher fb_div > & ref_div are pushing the PLL harder or faster? If you want details you should probably read them up on Wikipedia, but I will try to explain it in a few sentences. The basic problem is how to generate a stable but still programmable frequency in electronics. On the one hand you have crystals which are usually very stable over a long period of time, but to change the frequency of a crystal you would need to change it's size and/or the material it is made of. Clearly not something you can do with software. On the other hand you have voltage controllable oscillators (VCO), which have the nice feature that you can push a certain voltage into them and get a certain frequency in return. Problem with those is that they are not temperature stable, e.g. you set up a certain voltage to get 100Mhz and after a while the electronics has warmed up and you suddenly get 101Mhz or 99Mhz or something like this. The solution is a PLL, it compares a very stable input frequency to a frequency generated with a VCO and based on the difference adjusts the input voltage of the VCO. This way the VCO frequency is slowly adjusted to the stable input frequency and also stable over time when the electronics warms up. Imagine that you now put a counter between the VCO output and the comparator input that counts to 3 before forwarding the VCO frequency to the comparator. This way when you input a frequency of 100Mhz you get 300Mhz as output frequency. This counter is easily adjustable with software and called the feedback divider. So in the end you've got 300Mhz. But what do we do when for example we want 150Mhz? For this the electronics got a so called post divider it's also software configurable and when for example when you have 300Mhz VCO frequency and set the divider to 2 you get 150Mhz at the PLL output. The voltage given as input to the VCO needs to be in certain limits. The upper limit is easily understandable imagine that you push 20V into a 5V circuit all you usually get is blue smoke and useless electronics. The lower limit usually isn't so easily explainable, just keep in mind that the electronics need a certain voltage to start up. More rarely you also got voltage gaps where the VCO won't produce a stable output etc... So to stay within those limits you add a third divider which is put between the input frequency and the comparator. This divider is called the reference divider. Driving the PLL at the edge now means that at some point the VCO is to close to one of it's limits. E.g. when it startup the VCO usually doesn't match the input frequency at all and because of this the voltage input jumps around quite a bit. So it sometimes works and sometimes doesn't. Or it initially works but after the electronics has warmed up the VCO is suddenly out of range etc etc.... Maybe that were a few more sentences than I expected, hopefully it was still understandable. -- You are receiving this mail because: You are watching the assignee of the bug. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
