[PATCH v5 2/6] dt-bindings: gpu: v3d: Add per-compatible register restrictions

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In order to enforce per-SoC register rules, add per-compatible
restrictions. V3D 3.3 (used in brcm,7268-v3d) has a cache controller
(GCA), which is not present in other V3D generations. Declaring these
differences helps ensure the DTB accurately reflect the hardware design.

This commit breaks the ABI for BCM7268 to enforce an ascending address
order for registers. With a now well-defined ABI for different SoCs, the
goal is to maintain stability going forward.

Due to the change in the ABI, the example also needed to be updated.

Signed-off-by: Maíra Canal <mcanal@xxxxxxxxxx>
---
 .../devicetree/bindings/gpu/brcm,bcm-v3d.yaml      | 86 ++++++++++++++++++----
 1 file changed, 73 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
index dc078ceeca9ac3447ba54a7c8830821f0b2a7f9f..c736b3b00ed2c259c263615bdc2bc1899c8961f8 100644
--- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
+++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
@@ -22,20 +22,12 @@ properties:
       - brcm,7278-v3d
 
   reg:
-    items:
-      - description: hub register (required)
-      - description: core0 register (required)
-      - description: GCA cache controller register (if GCA controller present)
-      - description: bridge register (if no external reset controller)
     minItems: 2
+    maxItems: 4
 
   reg-names:
-    items:
-      - const: hub
-      - const: core0
-      - enum: [ bridge, gca ]
-      - enum: [ bridge, gca ]
     minItems: 2
+    maxItems: 4
 
   interrupts:
     items:
@@ -58,6 +50,74 @@ required:
   - reg-names
   - interrupts
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: brcm,2711-v3d
+    then:
+      properties:
+        reg:
+          items:
+            - description: hub register
+            - description: core0 register
+        reg-names:
+          items:
+            - const: hub
+            - const: core0
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: brcm,2712-v3d
+    then:
+      properties:
+        reg:
+          items:
+            - description: hub register
+            - description: core0 register
+        reg-names:
+          items:
+            - const: hub
+            - const: core0
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: brcm,7268-v3d
+    then:
+      properties:
+        reg:
+          items:
+            - description: hub register
+            - description: bridge register
+            - description: GCA cache controller register
+            - description: core0 register
+        reg-names:
+          items:
+            - const: hub
+            - const: bridge
+            - const: gca
+            - const: core0
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: brcm,7278-v3d
+    then:
+      properties:
+        reg:
+          items:
+            - description: hub register
+            - description: core0 register
+            - description: bridge register
+        reg-names:
+          items:
+            - const: hub
+            - const: core0
+            - const: bridge
+
 additionalProperties: false
 
 examples:
@@ -65,10 +125,10 @@ examples:
     gpu@f1200000 {
       compatible = "brcm,7268-v3d";
       reg = <0xf1200000 0x4000>,
-            <0xf1208000 0x4000>,
             <0xf1204000 0x100>,
-            <0xf1204100 0x100>;
-      reg-names = "hub", "core0", "bridge", "gca";
+            <0xf1204100 0x100>,
+            <0xf1208000 0x4000>;
+      reg-names = "hub", "bridge", "gca", "core0";
       interrupts = <0 78 4>,
                    <0 77 4>;
     };

-- 
Git-154)




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