On Sun, 23 Feb 2025 11:31:36 +0200, Cristian Ciocaltea wrote:
> As a followup to getting basic HDMI1 output support [1] merged upstream,
> make use of the HDMI1 PHY PLL to provide better VOP2 display modes
> handling for the second HDMI output port on RK3588 SoC, similarly to
> what has been achieved recently for HDMI0 [2].
>
> Please note Heiko's fix [3] in of_clk_get_hw_from_clkspec() is also
> required for boards that do not provide HDMI0 output, that is to ensure
> devm_clk_get_optional() returns NULL instead of ERR_PTR(-EPROBE_DEFER),
> which otherwise would put rockchip-drm module in a permanent deferred
> probe mode.
>
> [...]
Applied, thanks!
[3/5] arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588
commit: aadaa27956e3430217d9e6b8af5880e39b05b961
[4/5] arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588
commit: b2e668a60ed866ba960acb5310d1fb6bf81d154f
[5/5] arm64: dts: rockchip: Enable HDMI1 on rk3588-evb1
commit: 5c2d6181ae830e02856c603b8c08e80e9d419874
Best regards,
--
Heiko Stuebner <heiko@xxxxxxxxx>
