On Wed, Jan 29, 2025 at 12:55:04PM +0100, Krzysztof Kozlowski wrote:
> Since SM8250 all downstream sources program clock inverters in
> PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as
> reset value (0x0). The most recent Hardware Programming Guide for 3 nm,
> 4 nm, 5 nm and 7 nm PHYs also mention PLL_CLOCK_INVERTERS_1.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>
> ---
>
> Not tested except my work-in-progress oon SM8750. Not sure what is the
> impact, so also no Fixes tag.
I'd say,
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
I didn't fully test this, but according to msm-4.14, msm-4.19 and
display drivers techpack this change is required on all 7nm- PHYs
(including the SM8150).
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 7f6fb2a840d2..6646f8dbe457 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -326,7 +326,7 @@ static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *confi
> writel(pll->phy->cphy_mode ? 0x00 : 0x10,
> base + REG_DSI_7nm_PHY_PLL_CMODE_1);
> writel(config->pll_clock_inverters,
> - base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS);
> + base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1);
> }
>
> static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
> --
> 2.43.0
>
--
With best wishes
Dmitry
