On 29/01/2025 15:31, Dmitry Baryshkov wrote:
> On Wed, Jan 29, 2025 at 12:55:04PM +0100, Krzysztof Kozlowski wrote:
>> Since SM8250 all downstream sources program clock inverters in
>> PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as
>> reset value (0x0). The most recent Hardware Programming Guide for 3 nm,
>> 4 nm, 5 nm and 7 nm PHYs also mention PLL_CLOCK_INVERTERS_1.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>>
>> ---
>>
>> Not tested except my work-in-progress oon SM8750. Not sure what is the
>> impact, so also no Fixes tag.
>
> I'd say,
>
> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
>
> I didn't fully test this, but according to msm-4.14, msm-4.19 and
> display drivers techpack this change is required on all 7nm- PHYs
> (including the SM8150).
Thanks.
This was suggested to me in non-public talks so let's add original
credits as well:
Reported-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
Best regards,
Krzysztof
