On 12/04/2024, Biju Das wrote:
> Hi Liu Ying,
Hi Biju,
>
>> -----Original Message-----
>> From: Liu Ying <victor.liu@xxxxxxx>
>> Sent: 04 December 2024 03:43
>> Subject: Re: [PATCH] drm/bridge: ite-it6263: Support VESA input format
>>
>> On 12/04/2024, Dmitry Baryshkov wrote:
>>> On Tue, Dec 03, 2024 at 06:21:29PM +0100, tomm.merciai@xxxxxxxxx wrote:
>>>> From: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
>>>>
>>>> Introduce it6263_is_input_bus_fmt_valid() and refactor the
>>>> it6263_bridge_atomic_get_input_bus_fmts() function to support VESA
>>>> format by selecting the LVDS input format based on the LVDS data
>>>> mapping and thereby support both JEIDA and VESA input formats.
>>>
>>> For the patch itself,
>>>
>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
>>>
>>> A more generic question: is the bridge limited to 4 lanes or does it
>>> support 3-lane or 5-lane configurations?
>>
>> According to ite,it6263.yaml, the bridge supports all the data mappings(jeida-{18,24,30} and vesa-
>> {24,30}) listed in lvds-data-mapping.yaml. lvds-data-mapping.yaml specifies the data lanes(3/4/5)
>> used by each of the data mappings. So, the bridge supports 3, 4 or 5 data lanes.
>
> In Renesas SMARC RZ/G3E LVDS add on board, only 4 LVDS Rx lanes connected. The 5th one is unconnected.
> What is the situation in your board Liu Ying?
The adapter cards I'm using to connect with i.MX8MP EVK have only 4
LVDS data lanes routed out.
>
> Cheers,
> Biju
--
Regards,
Liu Ying
