On Tue, Dec 03, 2024 at 06:40:11PM +0100, Danylo Piliaiev wrote: > On at least a6xx+, shader could read 64b ALWAYSON counter > from UCHE_TRAP_BASE+0 address. In Mesa it will be used > to implement VK_KHR_shader_clock and GL_ARB_shader_clock. > These extensions provide shader functions to query a real-time or > monotonically incrementing counter at the subgroup level or > across the device level. > > On a4xx and a5xx it was not tested what is at UCHE_TRAP_BASE > address, there uche trap base is exposed just for completeness. > > Signed-off-by: Danylo Piliaiev <dpiliaiev@xxxxxxxxxx> > --- > Changes in v2: > - Rebased on top of https://patchwork.freedesktop.org/series/141667/ > in order to return error via UERR when there is no uche trap base. > - Updated commit message to explain why we need to expose the value. > > --- > drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 6 ++++-- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 10 ++++++---- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++----- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 +++++ > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++ > include/uapi/drm/msm_drm.h | 1 + > 6 files changed, 25 insertions(+), 11 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> Nit: in future please don't send new versions of the patch as a reply to the previous version. Please start a new thread for each new revision. -- With best wishes Dmitry
