Depends on https://patchwork.freedesktop.org/series/141667/ The parameter would be used in [1] to implement VK_KHR_shader_clock and GL_ARB_shader_clock. On at least a6xx+, shader could read 64b ALWAYSON counter from UCHE_TRAP_BASE+0 address. Downstream driver exposes uche trap base via uapi only on A7XX+. However, from testing, we could get correct shader clock on A6XX. The uche trap base value is not used by Mesa for A4XX and A5XX. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29860 Danylo Piliaiev (1): drm/msm: Expose uche trap base via uapi drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 6 ++++-- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 10 ++++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++----- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 +++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++ include/uapi/drm/msm_drm.h | 1 + 6 files changed, 25 insertions(+), 11 deletions(-) -- 2.46.2
