Hey,
Den 2024-12-03 kl. 09:50, skrev Jocelyn Falempe:
> This adds drm_panic support for a wide range of Intel GPU. I've
> tested it only on 3 laptops, haswell (with 128MB of eDRAM),
> cometlake and alderlake.
>
> * DPT: if I disable tiling on a framebuffer using DPT, then it
> displays some other memory location. As DPT is enabled only for
> tiled framebuffer, there might be some hardware limitations.
This is because DPT points to the pagetable, when you disable tiling DPT is no longer used so the DPT is interpreted as a linear FB instead of a lookup table.
The lookup table is necessarily smaller than the real FB, so you would need to overwrite part of the GGTT and point it to linear FB.
I'm not sure what the fix is here as it would require a real GGTT mapping to fix, needing an allocation which might not succeed. Perhaps indicates a limitation to require a real pageflip to fbdev fb?
Have you tested rotated by any chance? Cursor enabled? Overlay?
I also think this may fail if there are flips queued. We should probably bite the bullet, reprogram the entire state into a known state, disable all overlay planes and cursor, reassign all watermarks for the primary and ensure any background work is killed where needed.
Cheers,
~Maarten
> * fbdev: On my haswell laptop, the fbdev framebuffer is configured
> with tiling enabled, but really it's linear, because fbcon don't
> know about tiling, and the panic screen is perfect when it's drawn
> as linear.
> Signed-off-by: Jocelyn Falempe <jfalempe@xxxxxxxxxx>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 85 ++++++++++++++++++-
> 1 file changed, 84 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index b7e462075ded3..58eb3b4c55fa5 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -33,16 +33,20 @@
>
> #include <linux/dma-fence-chain.h>
> #include <linux/dma-resv.h>
> +#include <linux/iosys-map.h>
>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_blend.h>
> +#include <drm/drm_cache.h>
> #include <drm/drm_fourcc.h>
> #include <drm/drm_gem.h>
> #include <drm/drm_gem_atomic_helper.h>
> +#include <drm/drm_panic.h>
>
> #include "i915_config.h"
> #include "i9xx_plane_regs.h"
> #include "intel_atomic_plane.h"
> +#include "intel_bo.h"
> #include "intel_cdclk.h"
> #include "intel_cursor.h"
> #include "intel_display_rps.h"
> @@ -50,6 +54,7 @@
> #include "intel_display_types.h"
> #include "intel_fb.h"
> #include "intel_fb_pin.h"
> +#include "intel_fbdev.h"
> #include "skl_scaler.h"
> #include "skl_watermark.h"
>
> @@ -1198,14 +1203,92 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
> intel_plane_unpin_fb(old_plane_state);
> }
>
> +/* Only used by drm_panic get_scanout_buffer() and panic_flush(), so it is
> + * protected by the drm panic spinlock
> + */
> +static struct iosys_map panic_map;
> +
> +static void intel_panic_flush(struct drm_plane *plane)
> +{
> + struct intel_plane_state *plane_state = to_intel_plane_state(plane->state);
> + struct drm_i915_private *dev_priv = to_i915(plane->dev);
> + struct drm_framebuffer *fb = plane_state->hw.fb;
> + struct intel_plane *iplane = to_intel_plane(plane);
> +
> + /* Force a cache flush, otherwise the new pixels won't show up */
> + drm_clflush_virt_range(panic_map.vaddr, fb->height * fb->pitches[0]);
> +
> + /* Don't disable tiling if it's the fbdev framebuffer.*/
> + if (to_intel_framebuffer(fb) == intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev))
> + return;
> +
> + if (fb->modifier && iplane->disable_tiling)
> + iplane->disable_tiling(iplane);
> +}
> +
> +static int intel_get_scanout_buffer(struct drm_plane *plane,
> + struct drm_scanout_buffer *sb)
> +{
> + struct intel_plane_state *plane_state;
> + struct drm_gem_object *obj;
> + struct drm_framebuffer *fb;
> + struct drm_i915_private *dev_priv = to_i915(plane->dev);
> + void *ptr;
> +
> + if (!plane->state || !plane->state->fb || !plane->state->visible)
> + return -ENODEV;
> +
> + plane_state = to_intel_plane_state(plane->state);
> + fb = plane_state->hw.fb;
> + obj = intel_fb_bo(fb);
> + if (!obj)
> + return -ENODEV;
> +
> + if (to_intel_framebuffer(fb) == intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev)) {
> + ptr = intel_fbdev_get_vaddr(dev_priv->display.fbdev.fbdev);
> + } else {
> + /* can't disable tiling if DPT is in use */
> + if (intel_bo_is_tiled(obj) && HAS_DPT(dev_priv))
> + return -EOPNOTSUPP;
> +
> + ptr = intel_bo_panic_map(obj);
> + }
> +
> + if (!ptr)
> + return -ENOMEM;
> +
> + if (intel_bo_has_iomem(obj))
> + iosys_map_set_vaddr_iomem(&panic_map, ptr);
> + else
> + iosys_map_set_vaddr(&panic_map, ptr);
> +
> + sb->map[0] = panic_map;
> + sb->width = fb->width;
> + sb->height = fb->height;
> + sb->format = fb->format;
> + sb->pitch[0] = fb->pitches[0];
> +
> + return 0;
> +}
> +
> static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
> .prepare_fb = intel_prepare_plane_fb,
> .cleanup_fb = intel_cleanup_plane_fb,
> };
>
> +static const struct drm_plane_helper_funcs intel_primary_plane_helper_funcs = {
> + .prepare_fb = intel_prepare_plane_fb,
> + .cleanup_fb = intel_cleanup_plane_fb,
> + .get_scanout_buffer = intel_get_scanout_buffer,
> + .panic_flush = intel_panic_flush,
> +};
> +
> void intel_plane_helper_add(struct intel_plane *plane)
> {
> - drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
> + if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
> + drm_plane_helper_add(&plane->base, &intel_primary_plane_helper_funcs);
> + else
> + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
> }
>
> void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state,
