> > -----Original Message-----
> > From: Intel-xe <intel-xe-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> > Arun R Murthy
> > Sent: Tuesday, November 19, 2024 4:15 PM
> > To: intel-xe@xxxxxxxxxxxxxxxxxxxxx; intel-gfx@xxxxxxxxxxxxxxxxxxxxx;
> > dri- devel@xxxxxxxxxxxxxxxxxxxxx
> > Cc: Murthy, Arun R <arun.r.murthy@xxxxxxxxx>
> > Subject: [PATCH 6/8] drm/i915/histogram: histogram delay counter
> > doesnt reset
> >
> > The delay counter for histogram does not reset and as a result the
> > histogram bin never gets updated. Workaround would be to use save and
> > restore histogram register.
> > Wa: 14014889975
>
> This should be above the Signed-off-by
>
> >
> > Signed-off-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_histogram.c | 17
> > +++++++++++++++++ .../gpu/drm/i915/display/intel_histogram_regs.h | 1
> > +
> > 2 files changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c
> > b/drivers/gpu/drm/i915/display/intel_histogram.c
> > index cba65f4260cd..fdcc64677e96 100644
> > --- a/drivers/gpu/drm/i915/display/intel_histogram.c
> > +++ b/drivers/gpu/drm/i915/display/intel_histogram.c
> > @@ -74,6 +74,11 @@ static void intel_histogram_handle_int_work(struct
> > work_struct *work)
> > struct intel_display *display = to_intel_display(intel_crtc);
> > char *histogram_event[] = {"HISTOGRAM=1", NULL};
> >
> > + /* Wa: 14014889975 */
> > + if (IS_DISPLAY_VER(display, 12, 13))
>
> We have shifted to using is_display_verx100 so you can use that instead Also
> there is no display ver 13 just 12 and then 14 so maybe this should be just
> display_ver == 12
>
HSD mentioned above says display ver 13 ADL.
The commit 5eb2e7855910561a07d4cedf9c898624899b057b changes IS_DISPLAY_VER_FULL to IS_DISPLAY_VERx100
Here we are using IS_DISPLAY_VER()
>
> > + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe),
> > + DPST_CTL_RESTORE, 0);
> > +
> > /*
> > * TODO: PSR to be exited while reading the Histogram data
> > * Set DPST_CTL Bin Reg function select to TC @@ -94,6 +99,12 @@
> > static void intel_histogram_handle_int_work(struct work_struct *work)
> > "sending HISTOGRAM event failed\n");
> > }
> >
> > + /* Wa: 14014889975 */
> > + if (IS_DISPLAY_VER(display, 12, 13))
> > + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt
> > Delay Counter(bit 23:16) */
> > + intel_de_write(display, DPST_CTL(intel_crtc->pipe),
> > intel_de_read(display,
> > + DPST_CTL(intel_crtc->pipe)) |
> > DPST_CTL_RESTORE);
> > +
>
> From the WA it seems we need to write 0 in the above Guardband Interrupt
> Delay Counter (bits 23:16) when servicing interrupts And only write value read
> from dpst_ctl when enabling dpst_config or doing an adjustment
>
Done!
Thanks and Regards,
Arun R Murthy
--------------------
