On 11/14/24 7:57 AM, Liu Ying wrote:
This reverts commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155.
media_disp1_pix clock is the pixel clock of the first i.MX8MP LCDIFv3
display controller, while media_disp2_pix clock is the pixel clock of
the second i.MX8MP LCDIFv3 display controller. The two display
controllers connect with Samsung MIPI DSI controller and LVDS Display
Bridge(LDB) respectively. Since the two display controllers are driven
by separate DRM driver instances and the two pixel clocks may be derived
from the same video_pll1_out clock(sys_pll3_out clock could be already
used to derive audio_axi clock), there is no way to negotiate a dynamically
changeable video_pll1_out clock rate to satisfy both of the two display
controllers. In this case, the only solution to drive them with the
single video_pll1_out clock is to assign a sensible/unchangeable clock
rate for video_pll1_out clock. Thus, there is no need to set the
CLK_SET_RATE_PARENT flag for media_disp{1,2}_pix clocks, drop it then.
Fixes: ff06ea04e4cf ("clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate")
Signed-off-by: Liu Ying <victor.liu@xxxxxxx>
Uh, I almost missed this revert between all the LDB patches.
This revert will break my usecase on MX8MP where I need to operate two
disparate panels attached to LVDS and TC358767 DSI-to-DP bridge and I
need accurate pixel clock for both. Not being able to configure accurate
pixel clock will make the displays not work, so from my side, this is a
NAK, sorry.
There has to be some better solution which still allows the PLL
reconfiguration to achieve accurate pixel clock.
