On Wed, Oct 09, 2024 at 02:38:43PM GMT, Jun Nie wrote:
> Only 2 DSC engines are allowed, or no DSC is involved currently.
> We need 4 DSC in quad-pipe topology in future. So let's only configure
> DSC engines in use, instread of maximum number of DSC engines.
>
> Signed-off-by: Jun Nie <jun.nie@xxxxxxxxxx>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 39700b13e92f3..e8400b494687c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1871,10 +1871,13 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,
> ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
> }
>
> -static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> - struct drm_dsc_config *dsc)
> +static void dpu_encoder_prep_dsc(struct drm_encoder *drm_enc)
> {
> /* coding only for 2LM, 2enc, 1 dsc config */
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
> + struct dpu_crtc_state *cstate = to_dpu_crtc_state(drm_enc->crtc->state);
> + struct drm_dsc_config *dsc = dpu_enc->dsc;
> + int num_dsc = cstate->num_dscs;
I have been thinking about this part for a while. Please move num_dscs
to the dpu_encoder_virt structure. The DSC blocks are logically related
to the encoder, so having this field in dpu_crtc_state seems incorrect.
> struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
> struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
--
With best wishes
Dmitry
