On 10/9/24 12:27 PM, Isaac Scott wrote:
On Wed, 2024-10-09 at 00:38 +0200, Marek Vasut wrote:
The LDB serializer clock operate at either x7 or x14 rate of the
input
LCDIFv3 scanout engine clock. Make sure the serializer clock and
their
upstream Video PLL are configured early in .mode_set to the x7 or x14
rate of pixel clock, before LCDIFv3 .atomic_enable is called which
would
configure the Video PLL to low x1 rate, which is unusable.
With this patch in place, the clock tree is correctly configured. The
example below is for a 71.1 MHz pixel clock panel, the LDB serializer
clock is then 497.7 MHz:
Awesome! Thank you for this, this seems to fix the regression and the
patches work as expected. I have tested both patches on v6.12-rc2 and
the display works well.
For both patches,
Tested-by: Isaac Scott <isaac.scott@xxxxxxxxxxxxxxxx>
Thank you for testing, but this patch feels too much like a feature
development to me. Does the DT tweak I suggested also fix your issue? If
so, I would really like that DT tweak to be the fix for current release
and these two patches be feature development for 6.13 cycle. What do you
think ?
