From: Tomas Winkler <tomas.winkler@xxxxxxxxx>
Implement spi_read(), spi_erase() and spi_write() functions.
CC: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
CC: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Signed-off-by: Tomas Winkler <tomas.winkler@xxxxxxxxx>
Signed-off-by: Vitaly Lubart <vitaly.lubart@xxxxxxxxx>
Signed-off-by: Alexander Usyskin <alexander.usyskin@xxxxxxxxx>
---
drivers/spi/spi-intel-dg.c | 199 +++++++++++++++++++++++++++++++++++++
1 file changed, 199 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index 661e5189fa58..863898c8739c 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -3,13 +3,16 @@
* Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
*/
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/intel_dg_spi_aux.h>
#include <linux/io.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
+#include <linux/sizes.h>
#include <linux/types.h>
struct intel_dg_spi {
@@ -84,6 +87,33 @@ static inline u32 spi_read32(struct intel_dg_spi *spi, u32 address)
return ioread32(base + SPI_TRIGGER_REG);
}
+static inline u64 spi_read64(struct intel_dg_spi *spi, u32 address)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ return readq(base + SPI_TRIGGER_REG);
+}
+
+static void spi_write32(struct intel_dg_spi *spi, u32 address, u32 data)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ iowrite32(data, base + SPI_TRIGGER_REG);
+}
+
+static void spi_write64(struct intel_dg_spi *spi, u32 address, u64 data)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ writeq(data, base + SPI_TRIGGER_REG);
+}
+
static int spi_get_access_map(struct intel_dg_spi *spi)
{
u32 flmap1;
@@ -140,6 +170,175 @@ static int intel_dg_spi_is_valid(struct intel_dg_spi *spi)
return 0;
}
+__maybe_unused
+static unsigned int spi_get_region(const struct intel_dg_spi *spi, loff_t from)
+{
+ unsigned int i;
+
+ for (i = 0; i < spi->nregions; i++) {
+ if ((spi->regions[i].offset + spi->regions[i].size - 1) > from &&
+ spi->regions[i].offset <= from &&
+ spi->regions[i].size != 0)
+ break;
+ }
+
+ return i;
+}
+
+static ssize_t spi_rewrite_partial(struct intel_dg_spi *spi, loff_t to,
+ loff_t offset, size_t len, const u32 *newdata)
+{
+ u32 data = spi_read32(spi, to);
+
+ if (spi_error(spi))
+ return -EIO;
+
+ memcpy((u8 *)&data + offset, newdata, len);
+
+ spi_write32(spi, to, data);
+ if (spi_error(spi))
+ return -EIO;
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t spi_write(struct intel_dg_spi *spi, u8 region,
+ loff_t to, size_t len, const unsigned char *buf)
+{
+ size_t i;
+ size_t len8;
+ size_t len4;
+ size_t to4;
+ size_t to_shift;
+ size_t len_s = len;
+ ssize_t ret;
+
+ spi_set_region_id(spi, region);
+
+ to4 = ALIGN_DOWN(to, sizeof(u32));
+ to_shift = min(sizeof(u32) - ((size_t)to - to4), len);
+ if (to - to4) {
+ ret = spi_rewrite_partial(spi, to4, to - to4, to_shift,
+ (uint32_t *)&buf[0]);
+ if (ret < 0)
+ return ret;
+
+ buf += to_shift;
+ to += to_shift;
+ len_s -= to_shift;
+ }
+
+ len8 = ALIGN_DOWN(len_s, sizeof(u64));
+ for (i = 0; i < len8; i += sizeof(u64)) {
+ u64 data;
+
+ memcpy(&data, &buf[i], sizeof(u64));
+ spi_write64(spi, to + i, data);
+ if (spi_error(spi))
+ return -EIO;
+ }
+
+ len4 = len_s - len8;
+ if (len4 >= sizeof(u32)) {
+ u32 data;
+
+ memcpy(&data, &buf[i], sizeof(u32));
+ spi_write32(spi, to + i, data);
+ if (spi_error(spi))
+ return -EIO;
+ i += sizeof(u32);
+ len4 -= sizeof(u32);
+ }
+
+ if (len4 > 0) {
+ ret = spi_rewrite_partial(spi, to + i, 0, len4,
+ (uint32_t *)&buf[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t spi_read(struct intel_dg_spi *spi, u8 region,
+ loff_t from, size_t len, unsigned char *buf)
+{
+ size_t i;
+ size_t len8;
+ size_t len4;
+ size_t from4;
+ size_t from_shift;
+ size_t len_s = len;
+
+ spi_set_region_id(spi, region);
+
+ from4 = ALIGN_DOWN(from, sizeof(u32));
+ from_shift = min(sizeof(u32) - ((size_t)from - from4), len);
+
+ if (from - from4) {
+ u32 data = spi_read32(spi, from4);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[0], (u8 *)&data + (from - from4), from_shift);
+ len_s -= from_shift;
+ buf += from_shift;
+ from += from_shift;
+ }
+
+ len8 = ALIGN_DOWN(len_s, sizeof(u64));
+ for (i = 0; i < len8; i += sizeof(u64)) {
+ u64 data = spi_read64(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+
+ memcpy(&buf[i], &data, sizeof(data));
+ }
+
+ len4 = len_s - len8;
+ if (len4 >= sizeof(u32)) {
+ u32 data = spi_read32(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[i], &data, sizeof(data));
+ i += sizeof(u32);
+ len4 -= sizeof(u32);
+ }
+
+ if (len4 > 0) {
+ u32 data = spi_read32(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[i], &data, len4);
+ }
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t
+spi_erase(struct intel_dg_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr)
+{
+ u64 i;
+ const u32 block = 0x10;
+ void __iomem *base = spi->base;
+
+ for (i = 0; i < len; i += SZ_4K) {
+ iowrite32(from + i, base + SPI_ADDRESS_REG);
+ iowrite32(region << 24 | block, base + SPI_ERASE_REG);
+ /* Since the writes are via sguint
+ * we cannot do back to back erases.
+ */
+ msleep(50);
+ }
+ return len;
+}
+
static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device)
{
int ret;
--
2.34.1
