Quoting Alexandre Mergnat (2024-04-18 07:17:00)
> To have a working display through DPI, a workaround has been
> implemented downstream to add "mm_dpi0_dpi0" and "dpi0_sel" to
> the DPI node. Shortly, that add an extra clock.
>
> It seems consistent to have the "dpi0_sel" as parent.
> Additionnaly, "vpll_dpix" isn't used/managed.
>
> Then, set the "mm_dpi0_dpi0" parent clock to "dpi0_sel".
>
> The new clock tree is:
>
> clk26m
> lvdspll
> lvdspll_X (2, 4, 8, 16)
> dpi0_sel
> mm_dpi0_dpi0
>
> Fixes: d46adccb7966 ("clk: mediatek: add driver for MT8365 SoC")
> Signed-off-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx>
> ---
Applied to clk-next
