Il 18/04/24 16:17, Alexandre Mergnat ha scritto:
To have a working display through DPI, a workaround has been
implemented downstream to add "mm_dpi0_dpi0" and "dpi0_sel" to
the DPI node. Shortly, that add an extra clock.
It seems consistent to have the "dpi0_sel" as parent.
Additionnaly, "vpll_dpix" isn't used/managed.
Then, set the "mm_dpi0_dpi0" parent clock to "dpi0_sel".
The new clock tree is:
clk26m
lvdspll
lvdspll_X (2, 4, 8, 16)
dpi0_sel
mm_dpi0_dpi0
Fixes: d46adccb7966 ("clk: mediatek: add driver for MT8365 SoC")
Signed-off-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx>
I wonder what CLK_TOP_VPLL_DPIX_EN is for, but since you've ruled it out
by removing the dependency, this clock is 100% being disabled because unused
and the DPI interface clearly still works.
I also wonder if that clock is getting en/disabled by HW control mechanism...
...because that'd make sense, as this is .. well, a DPI clock.
That's just out of curiosity though, as I'd really like to understand whenwhatwhy
for stuff....
In any case, whether you have an answer or not, this commit is:
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
Cheers!
