Hi Robert On Tue, Mar 5, 2024 at 3:54 PM Robert Foss <rfoss@xxxxxxxxxx> wrote: > > On Tue, 28 Mar 2023 22:37:51 +0530, Jagan Teki wrote: > > For a given bridge pipeline if any bridge sets pre_enable_prev_first > > flag then the pre_enable for the previous bridge will be called before > > pre_enable of this bridge and opposite is done for post_disable. > > > > These are the potential bridge flags to alter bridge init order in order > > to satisfy the MIPI DSI host and downstream panel or bridge to function. > > However the existing pre_enable_prev_first logic with associated bridge > > ordering has broken for both pre_enable and post_disable calls. > > > > [...] > > Please excuse the delay, patches touching the core bridge code are a little > bit tougher to merge due to increased risks of breaking unrelated things. > > Applied, thanks! > I have a question about this prev_first flag. Can we map the order in the connector in dts? Michael > [1/2] drm/bridge: Fix improper bridge init order with pre_enable_prev_first > https://cgit.freedesktop.org/drm/drm-misc/commit/?id=e18aeeda0b69 > [2/2] drm/bridge: Document bridge init order with pre_enable_prev_first > https://cgit.freedesktop.org/drm/drm-misc/commit/?id=113cc3ad8566 > > > > Rob > > -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@xxxxxxxxxxxxxxxxxxxx __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@xxxxxxxxxxxxxxxxxxxx www.amarulasolutions.com
