Hi Frank, On Mon, Feb 05, 2024 at 04:22:28PM +0100, Frank Oltmanns wrote: > This panel is used in the pinephone that runs on a Allwinner A64 SOC. > The SOC requires pll-mipi to run at more than 500 MHz. > > This is the relevant clock tree: > pll-mipi > tcon0 > tcon-data-clock > > tcon-data-clock has to run at 1/4 the DSI per-lane bit rate. The XBD599 > has 24 bpp and 4 lanes. Therefore, the resulting requested > tcon-data-clock rate is: > crtc_clock * 1000 * (24 / 4) / 4 > > tcon-data-clock runs at tcon0 / 4 (fixed divisor), so it requests a > parent rate of > 4 * (crtc_clock * 1000 * (24 / 4) / 4) > > Since tcon0 is a ccu_mux, the rate of tcon0 equals the rate of pll-mipi. > > pll-mipi's constraint to run at 500MHz or higher forces us to have a > crtc_clock >= 83333 kHz if we want a 60 Hz vertical refresh rate. > > Change [hv]sync_(start|end) so that we reach a clock rate of 83502 kHz > so that it is high enough to align with pll-pipi limits. > > Signed-off-by: Frank Oltmanns <frank@xxxxxxxxxxxx> That commit log is great, but it's kind of off-topic. It's a panel driver, it can be used on any MIPI-DSI controller, the only relevant information there should be the panel timings required in the datasheet. The PLL setup is something for the MIPI-DSI driver to adjust, not for the panel to care for. Maxime
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