Hi Diederik,
On Fri, Dec 22, 2023 at 06:01:54PM +0100, Diederik de Haas wrote:
> On Friday, 22 December 2023 12:05:44 CET Manuel Traut wrote:
> > +
> > +&cru {
> > + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru
> > PLL_VPLL>; + assigned-clock-rates = <1200000000>, <200000000>,
> > <500000000>; +};
>
> Attachment seem to work and for this I also have the attached patch in my
> patch set.
> IIRC without it you get an error in dmesg immediately at boot up which is
> visible on the PT2 *if* you have immediate visual output (which is not (yet?)
> the case in my image/kernel).
you can see the message also by calling "dmesg --level err".
I could verify that your patch removes the error message.
I will pick the change for v2.
> Cheers,
> Diederik
> From d782a64f3b51ffb2f33d3ba3e11e2ebc416542e3 Mon Sep 17 00:00:00 2001
> From: Jonas Karlman <jonas@xxxxxxxxx>
> Date: Thu, 17 Aug 2023 17:52:47 +0200
> Subject: [PATCH 6/8] arm64: dts: rk3566-pinetab2: Fix cru assigned clocks
>
> Jonas Karlman provided/linked to the patch on IRC.
> Seems related to upstream commit 64b69474edf3b885c19a89bb165f978ba1b4be00.
>
> Signed-off-by: Diederik de Haas <didi.debian@xxxxxxxxx>
> Link: https://github.com/Kwiboo/u-boot-rockchip/blob/rk3568-2023.10/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi#L11-L15
> Link: https://lore.kernel.org/all/20230110225547.1563119-2-jonas@xxxxxxxxx/
> ---
> arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi
> index bbd7ed53602a..4a5bee5a28a7 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi
> @@ -288,8 +288,9 @@ &cpu3 {
> };
>
> &cru {
> - assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
> - assigned-clock-rates = <1200000000>, <200000000>, <500000000>;
> + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
> + assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>;
> + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
> };
>
> &csi_dphy {
> --
> 2.42.0
>
