On Wed, Nov 01, 2023 at 06:26:47AM +0000, Hogander, Jouni wrote: > On Tue, 2023-10-31 at 23:21 +0000, Paz Zcharya wrote: > > Currently, i915 fails fastset if both the sink and the source support > > any version of PSR and regardless of the configuration setting of the > > driver (i.e., i915.enable_psr kernel argument). However, the > > implementation of PSR1 enable sequence is already seamless > > and works smoothly with fastset. Accordingly, do not fail fastset > > if PSR2 is not enabled. > > Thank you for the patch. Check similar patch I sent some time ago to > trybot: > > https://patchwork.freedesktop.org/series/125392/ > I missed this patch. I apologize! This is great work and exactly what we (Google ChromeOS) need. I think your patch is better than mine, so let's abort my patch and continue the discussion at series/125392. By the way, we have verified your patch on two Meteor Lake devices running ChromeOS and it works smoothly (no flickering or modesets). I'll comment on the other patch as well. > If we want to temporarily do this only for psr1 I think you could check > what I've done in drivers/gpu/drm/i915/display/intel_display.c in my > patch and modify your patch accordingly. Otherwise e.g. our IGT > testcases which are toggling PSR enable/disable/psr1/psr2 are to my > understanding performing full modeset and possible issues are not > revealed. > > After modifying drivers/gpu/drm/i915/display/intel_display.c you can > also verify it is really seamless and smooth by toggling different PSR > states via /sys/kernel/debug/dri/0/i915_edp_psr_debug. That interface > is performing atomic commit when PSR mode is changed. > > BR, > > Jouni Högander > > > > Signed-off-by: Paz Zcharya <pazz@xxxxxxxxxx> > > --- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- > > drivers/gpu/drm/i915/display/intel_psr.c | 2 +- > > drivers/gpu/drm/i915/display/intel_psr.h | 1 + > > 3 files changed, 4 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index e0e4cb529284..a1af96e31518 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct > > intel_encoder *encoder, > > fastset = false; > > } > > > > - if (CAN_PSR(intel_dp)) { > > - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full > > modeset to compute PSR state\n", > > + if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) { > > + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full > > modeset due to PSR2\n", > > encoder->base.base.id, encoder- > > >base.name); > > crtc_state->uapi.mode_changed = true; > > fastset = false; > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 97d5eef10130..388bc3246db9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp > > *intel_dp) > > } > > } > > > > -static bool psr2_global_enabled(struct intel_dp *intel_dp) > > +bool psr2_global_enabled(struct intel_dp *intel_dp) > > { > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h > > b/drivers/gpu/drm/i915/display/intel_psr.h > > index 0b95e8aa615f..6f3c36389cd3 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.h > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h > > @@ -21,6 +21,7 @@ struct intel_encoder; > > struct intel_plane; > > struct intel_plane_state; > > > > +bool psr2_global_enabled(struct intel_dp *intel_dp); > > void intel_psr_init_dpcd(struct intel_dp *intel_dp); > > void intel_psr_pre_plane_update(struct intel_atomic_state *state, > > struct intel_crtc *crtc); > .
