Hi Nirmoy,
> + if (aux_inv) {
> + u32 bit_group_0 = 0;
> + u32 bit_group_1 = 0;
> +
> + cmd += 4;
> +
> + bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
> +
> + switch (rq->engine->class) {
> + case VIDEO_DECODE_CLASS:
> + bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> + bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + bit_group_1 |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> + bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
> + bit_group_1 |= PIPE_CONTROL_CS_STALL;
> +
> + intel_emit_pipe_control_cs(rq, bit_group_0, bit_group_1,
> + LRC_PPHWSP_SCRATCH_ADDR);
>
>
> I think pipe control is only for compute and render engines.
>
> +
> + break;
> +
> + case VIDEO_ENHANCEMENT_CLASS:
> + case COMPUTE_CLASS:
>
> Don't think gen12_emit_flush_xcs() will get called for compute engine.
>
> intel_guc_submission_setup() --> rcs_submission_override() replaces
> gen12_emit_flush_xcs() with gen12_emit_flush_rcs()
>
> for compute and render.
yes, I made some confusion here... this part is bogus... will try
to clean things up and try again.
Andi
