On Saturday, June 24, 2023 10:17:57 AM PDT Lucas De Marchi wrote:
> The comment on the parameter being 0 to avoid the read back doesn't
> apply as this is not a call to wa_mcr_add(), but rather to
> wa_mcr_clr_set(). So, this register is actually checked and it's
> according to the Bspec that the register is RW, not RO.
I think you mean wa_add and wa_write_clr_set here (not mcr).
One thing I've been confused about while reading this code:
static void
wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
{
wa_add(wal, reg, clear, set, clear, false);
}
The second to last parameter is read_mask aka wa->read. We're
initializing it to the...bits to clear. (I would think it should be
(clear | set) to pick up all modified bits.)
wa_verify seems to balk at ((cur ^ wa->set) & wa->read). But...if
wa->read is just the clear mask, that wouldn't actually verify that
any bits were set at all. Or am I misunderstanding something?
If not, we may be failing to verify the majority of our workarounds :(
> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 848519b58e45..5fe85fad91c1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -666,7 +666,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> /* Wa_1604278689:icl,ehl */
> wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
> wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER,
> - 0, /* write-only register; skip validation */
> + 0,
> 0xFFFFFFFF);
>
> /* Wa_1406306137:icl,ehl */
In this particular example, since clear bits are 0, I don't think any
verification is happening at all.
--Ken
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