On Mon, May 15, 2023 at 02:22:52PM +0200, AngeloGioacchino Del Regno wrote: > > +#define CSIxB_OFFSET 0x1000 > > What if we grab two (or three?) iospaces from devicetree? > > - base (global) > - csi_a > - csi_b > > That would make it possible to maybe eventually extend this driver to more > versions (older or newer) of the CSI PHY IP without putting fixes offsets > inside of platform data structures and such. > Hi Angelo, The register bank of the CSI port is divided into 2: * from base address to base + 0x1000 (port A) * from base + 0x1000 to base +0x2000 (port B) Some CSI port can be configured in 4D1C mode (4 data + 1 clock) using the whole register bank from base to base + 0x2000 or in 2D1C mode (2 data + 1 clock) and use either port A or port B. For example mt8365 has CSI0 that can be used either in 4D1C mode or in 2 * 2D1C and CSI1 which can use only 4D1C mode 2D1C mode can not be tested and is not implemented in the driver so I guess adding csi_a and csi_b reg value may be confusing? What do you think? Regards, Julien
