On Thu, Apr 27, 2023 at 4:35 PM Francesco Dolcini <francesco@xxxxxxxxxx> wrote:
>
> From: Francesco Dolcini <francesco.dolcini@xxxxxxxxxxx>
>
> According to Toshiba documentation the PLL input clock after the divider
> should be not less than 4MHz, fix the PLL parameters computation
> accordingly.
>
> Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver")
> Signed-off-by: Francesco Dolcini <francesco.dolcini@xxxxxxxxxxx>
> ---
> drivers/gpu/drm/bridge/tc358768.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c
> index 8f349bf4fc32..e9e3f9e02bba 100644
> --- a/drivers/gpu/drm/bridge/tc358768.c
> +++ b/drivers/gpu/drm/bridge/tc358768.c
> @@ -334,13 +334,17 @@ static int tc358768_calc_pll(struct tc358768_priv *priv,
> u32 fbd;
>
> for (fbd = 0; fbd < 512; ++fbd) {
> - u32 pll, diff;
> + u32 pll, diff, pll_in;
>
> pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
>
> if (pll >= max_pll || pll < min_pll)
> continue;
>
> + pll_in = (u32)div_u64((u64)refclk, prd + 1);
> + if (pll_in < 4000000)
> + continue;
> +
> diff = max(pll, target_pll) - min(pll, target_pll);
>
> if (diff < best_diff) {
> --
> 2.25.1
>
Reviewed-by: Robert Foss <rfoss@xxxxxxxxxx>
